LG -E450 Service Manual page 204

PCB Revision
ADC
R301
+2V85_VRF_MTK PCB_REVISION
100K
R1
R302
47K
R2
Seperate DC-DC GND to Main GND
VBATT
VBATT
P8
VBAT_SPK1
P7
VBAT_SPK2
P5
VBI_P
N5
VBI_N
N3
AUD1_P
N4
AUD1_N
P2
AUD2_P
P3
AUD2_N
1u M5
C323 BYPASS
P13
SPK1_P
P12
SPK1_N
P10
SPK2_P
P11
SPK2_N
1%
R310 330k N1
VCDT
VCHG_LDO_4V9
R311 3.3K H5
CHR_LDO
L1
VDRV
R312 H1
C332 VBATT ISENSE
1% H2
BATSNS
2.2u
K1
39K BATT_TEMP_ADC BATON
J3
VTREF TREF
M2
PCH_DET
K3
USB_DLN
L3
USB_DLP
A2
SRCLKENA SRCLKEN
AVDD18_DIG L2
RESET_IN RESETB
N2
PWR_ON_SW_N PWRKEY
M4
PMU_TESTMODE
M3
BBWAKEUP PWRBB
B4
WATCHDOG_RESET SYSRSTB
A4
FSOURCE
D3
SCL_2 SCK
D2
SDA_2 SDA
B3
PMU_INT INT
C1
PMUCTRL0 DVS1
C4
PMUCTRL1 DVS2
B2
PACTRL0 PA_SEL0
C3
PACTRL1 PA_SEL1
B1
PACTRL2 PA_SEL2
A3
BL_PWM
E6
HOMEKEY
G1
CS+
G2
FGN_IC CS-
K5
R333
32K_IN
100
RTCCLK_D
LGE Internal Use Only
+1V2_VLPDDR2_MTK
Revision R1 R2 ADC Value[V]
A 100K 5.6K 0.151136
B 100K 12K 0.305357
0.457053
C 100K 19.1K
D 100K 27K 0.605906
1.0 100K 47K 0.911224
1.1 100K 100K 1.425
1.2 100K 250K 2.035714
+1V8_VIO_MTK
AVDD18_DIG
F12 L300 2.2u
VCORE_1
F13
VCORE_2
E12
VCORE_3
4.7u
B12 C318
VCORE_FB
C14 L301 2.2u
VPROC_1
D13 C321 4.7u
VPROC_2
D14
VPROC_3
C322 10n
E10
VPROC_FB VAPROC_FB
G12 L302 2.2u
VIO18_1
G13
VIO18_2 C334 4.7u
D300
A13
VIO18_FB
J13 L303 4.7u
VPA_1
K13
VPA_2
C12
U301 VPA_FB
L304 2.2u
H12
VRF18 +1V8_VRF_MTK
C330 4.7u
D12
VRF18_FB
FOR PI TEST
A10 R331
1.2V,300mA VM12_1
C9
0.9-1.2V,300mA VM12_2 1
B10
1.2V,360mA VM12_INT
E1
2.85V,200mA VRF28
F5
2.8V,40mA VTCXO
E3
1.8-2.5V,100mA VA1
B9
2.8V,100mA VIO28
A8
1.8/3.0V,100mA VSIM
C8
1.3-3.3V,100mA VSIM2
C10
1.3-3.3V,200mA VMC
A11
1.3-3.3V,400mA VMCH
B7
1.3-3.3V,200mA VGP
B11
1.3-3.3V,100mA VGP2
B8
3.3V,100mA VUSB
F2
1.5-2.8V,200mA VCAMA
F3
VCAMA_S
A7
1.3-3.3V,200mA VCAM_AF
B5
1.3-3.3V,300mA VCAMD
A5
1.3-3.3V,100mA VCAM_IO
B6
1.3-3.3V,100mA VIBR
G3
2.5/2.8V,100mA VA2
G5
VA2_BUF
E7
1.8-2.8V,2mA VRTC
J2
C336 1u
VRET
K2 C338
GND_VREF
1u
J5
CHG_DP CHD_DP
H3
CHG_DM CHD_DM
[4GB eMMC_4Gb LPDDR2] FOR V5
+1V8_VIO_MTK
H5
DDRAM_DATA_[28] DQ28
T8
DDRAM_DATA_[0] TP301 DQ0
R8
DDRAM_DATA_[1] DQ1
K7
DDRAM_DATA_[10] DQ10
J6
DDRAM_DATA_[11] DQ11
J9
DDRAM_DATA_[12] DQ12
J7
DDRAM_DATA_[13] DQ13
J8
DDRAM_DATA_[14] DQ14
H8
DDRAM_DATA_[15] DQ15
W7
DDRAM_DATA_[16] DQ16
U6
DDRAM_DATA_[17] DQ17
W8
DDRAM_DATA_[18] DQ18
T5
DDRAM_DATA_[19] DQ19
R7
DDRAM_DATA_[2] DQ2
U7
DDRAM_DATA_[20] DQ20
W9
DDRAM_DATA_[21] DQ21
V8
DDRAM_DATA_[22] DQ22
T6
DDRAM_DATA_[23] DQ23
H6
DDRAM_DATA_[24] DQ24
F8
DDRAM_DATA_[25] DQ25
E9
DDRAM_DATA_[26] DQ26
G7 H9TP32A4GDBCPR-KGM
DDRAM_DATA_[27] DQ27
E8
DDRAM_DATA_[29] DQ29
R9
DDRAM_DATA_[3] DQ3
G6
DDRAM_DATA_[30] DQ30
E7
DDRAM_DATA_[31] DQ31
R6
DDRAM_DATA_[4] DQ4
P7
DDRAM_DATA_[5] DQ5
P8
DDRAM_DATA_[6] DQ6
P9
DDRAM_DATA_[7] DQ7
K9
DDRAM_DATA_[8] DQ8
K8
DDRAM_DATA_[9] DQ9
P5
DDRAM_DQS_[0]_N DQS0_C
P6
DDRAM_DQS_[0]_P DQS0_T
K5
DDRAM_DQS_[1]_N DQS1_C
K6
DDRAM_DQS_[1]_P DQS1_T
EAN62577401
U9
DDRAM_DQS_[2]_N DQS2_C
U8
DDRAM_DQS_[2]_P DQS2_T
G9
DDRAM_DQS_[3]_N DQS3_C
G8
DDRAM_DQS_[3]_P DQS3_T
N5
DDRAM_DQM_[0] DM0
L5
DDRAM_DQM_[1] DM1
T7
DDRAM_DQM_[2] DM2
H7
DDRAM_DQM_[3] DM3
+1V2_CORE_MTK
+1V35_PROC_MTK
+1V8_VIO_MTK
VBATT
+3V4_VWPAM_MTK
C362
2.2u
+1V2_VLPDDR2_MTK
+1V2_VM12_INT_MTK
+2V85_VRF_MTK
+2V8_VTCXO_MTK
+2V5_AVDD1_MTK
+2V8_VIO_MTK
+3V0_VSIM_MTK
+3V0_VSIM2_MTK
+3V3_eMMC_MTK
+3V3_MICRO_SD
+3V3_MICRO_IO
+3V0_TOUCH_MTK
+3V3_USB_MTK
+3V0_PROX_MTK
+3V0_SENSORS_MTK
+2V8_LCD_VCI_MTK
+1V8_LCD_VIO_MTK
+3V0_VIBR_MTK
+2V5_AVDD2_MTK
+2V8_VRTC_MTK
- 204 -
+1V8_VIO_MTK
+0V6_VREF
+3V3_eMMC_MTK
U3
CA0
DDRAM_ADDRESS_[0]
T3
CA1
DDRAM_ADDRESS_[1]
R3
CA2
DDRAM_ADDRESS_[2]
R2
CA3
DDRAM_ADDRESS_[3]
R1
CA4
DDRAM_ADDRESS_[4]
K2
CA5
DDRAM_ADDRESS_[5]
J2
CA6
DDRAM_ADDRESS_[6]
J3
CA7
DDRAM_ADDRESS_[7]
H3
CA8
DDRAM_ADDRESS_[8]
H2
CA9 DDRAM_ADDRESS_[9]
G3
U302 ZQ0
F3
NC18
L3
CLK_C DDRAM_CLK_N
M3
CLK_T DDRAM_CLK_P
N1
CKE0 DDRAM_CLK_EN
N2
NC19
P1
CS0 DDRAM_CS_[0]_N
P2
NC20 DDRAM_CS_[1]_N
L2
VSS
A3
DAT0
B3
DAT1
B7
DAT2
A7
DAT3
B6
DAT4
A6
DAT5
A4
DAT6
B4
DAT7
C1
RST
C5
CMD
B5 R322
CLKM eMMC_CLK
33
R320
+1V8_VIO_MTK
10K
Copyright © 2013 LG Electronics. Inc. All right reserved.
7. CIRCUIT DIAGRAM
+1V2_VLPDDR2_MTK
+0V6_VREF
+1V8_VIO_MTK
eMMC_DATA[0]
eMMC_DATA[1]
eMMC_DATA[2]
eMMC_DATA[3]
eMMC_DATA[4]
eMMC_DATA[5]
eMMC_DATA[6]
eMMC_DATA[7]
eMMC_RST
eMMC_CMD
Only for training and service purposes