Figure 5.1-2 - Single Stage Circuit Breaker Fail Timing; Figure 5.1-3 - Two Stage Circuit Breaker Fail Timing - Siemens 7SR21 Manual

The time delays run concurrently within the relay. The time delay applied to the CB Fail protection must be in
excess of the longest CB operate time + relay reset time + a safety margin.
First Stage (Retrip)
Trip Relay operate time
Reset Time
CB Tripping time
Safety Margin
Overall First Stage CBF Time Delay
Second Stage (Back Trip)
First CBF Time Delay
Trip Relay operate time
CB Tripping time
Reset Time of measuring element
Margin
Overall Second Stage CBF Time Delay
The safety margin is extended by 1 cycle for the second CBF stage as this will usually involve a back-trip of a
Busbar tripping scheme.
The timing sequence for each stage of the circuit breaker fail function is as below.
Relay
Operation
and CBF
Timer
Started
System
Fault
Main
Trip
Failure of
Relay
CB to trip
Operation
20 40 60
CB Operate Time
Stage 1 CBF Timer (Backtrip) = 120ms
Relay
Operation
and CBF
Timer
Started
System
Fault
Main
CB's
Trip
Fails to
Relay
Trip
Operation
40 60
CB Operate Time
Stage 1 CBF Timer (Retrip) = 120ms
©2010 Siemens Protection Devices Limited
Backtrip
Trip Relay
Reset of
CBF elements
Backtrip
does not occur
Operation
80 100 120 140 160

Figure 5.1-2 - Single Stage Circuit Breaker Fail Timing

CBF Retrip
Trip Relay
No Reset of
CBF Retrip
CBF elements
Operation
80 100 120 140 160
Stage 2 CBF Timer (Backtrip) = 250ms

Figure 5.1-3 - Two Stage Circuit Breaker Fail Timing

7SR21 & 7SR22 Argus Applications Guide
10ms
20ms
50ms
40ms
120ms
120ms
10ms
50ms
20ms
60ms
260ms
CB Backtrip
Sucessful
180 200 220 240 260
No Reset of
CBF elements
CBF Back trip
Failed CB Retrip
Operation
Operation
180 200 220 240 260
280 300 320 340
Backtrip
Operation of all
Trip Relay
BB CB's
Operation
Reset of
CBF elements
280 300 320 340 360
Chapter 7 Page 34 of 39
ms from fault
occuring
ms from
occuri