Sharp SD-AT1000 Service Manual page 46

SD-AT1000
IC102 VHiAK4586VQ-1: ADC/DAC/DIR Converter (AK4586VQ) (1/2)
Pin No. Terminal Name
1* XTO
2 XTI
EXTCLK
3 TVDD
4 DVSS
5 DVDD
6* TX
7 MCKO
8 LRCK
9 BICK
10 SDTO
11 SDTI1
12 SDTI2
13 SDTI3
14* INT0
15 INT1
16 CDTO
CAD1
17 CDTI
SDA
18 CCLK
SCL
19 CSN
CAD0
20 DZF2
OVF
21 AVSS
22 AVDD
23 VREFH
24 VCOM
25* DZF1
26 LOUT3
27 ROUT3
28 LOUT2
29 ROUT2
30 LOUT1
31 ROUT1
32 LIN
33 RIN
34 PVDD
35 R
36 PVSS
37* RX4
38 SLAVE
39* RX3
40 TST
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
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Input/Output
Output Crystal resonator output pin.
Input Crystal resonator input pin.
Input Master clock input pin.
Input Power supply pin for the output buffer. 2.7 V – 5.5 V.
— Digital ground pin. 0 V.
Input Digital power supply pin. 4.5 V – 5.5 V.
Output Transmit channel (through data) output pin.
Output Master clock output pin.
Input/Output Input/output channel clock pin.
Input/Output Audio serial data clock pin.
Output Audio serial data output pin.
Input DAC1 audio serial data input pin.
Input DAC2 audio serial data input pin.
Input DAC3 audio serial data input pin.
Output Interrupt 0 pin.
Output Interrupt 1 pin.
Output Control data output pin. (In the 4-line serial mode)
Input Chip address 1 pin. (In the I
Input Control data input pin. (In the 4-line serial mode)
Input/Output Control data input/output pin. (In the I
Input Control data clock pin. (In the 4-line serial mode)
Input Control data clock pin. (In the I
Input Chip select pin. (In the 4-line serial mode)
Input Chip address 0 pin. (In the I
Output Zero input detect 2 pin. (Note 1)
When the input data of group 2 is "0" for 8192 times in a row or the RSTN bit is "0", it
changes to "H".
Output Analog input overflow detect pin. (Note 2)
It changes to "H" if the analog input of Lch or Rch overflows.
— Analog ground pin. 0 V.
Input Analog power supply pin. 4.5 V – 5.5 V.
Input Reference voltage input pin. AVDD.
Output Common voltage output pin. AVDD/2.
Output Zero input detect 1 pin. (Note 1)
When the input data of group 1 is "0" for 8192 times in a row or the RSTN bit is "0", it
changes to "H".
Output DAC3 L channel analog output pin.
Output DAC3 R channel analog output pin.
Output DAC2 L channel analog output pin.
Output DAC2 R channel analog output pin.
Output DAC1 L channel analog output pin.
Output DAC1 R channel analog output pin.
Input L channel analog input pin.
Input R channel analog input pin.
Input PLL power supply pin. 4.5 V – 5.5 V.
— External resistor pin.
— PLL ground pin. 0 V.
Input Receiver channel input 4 pin. (Internal bias pin)
Input Slave mode pin. "L" : master mode or slave mode, "H" : slave mode
Input Receiver channel input 3 pin. (Internal bias pin)
Input Test pin. Connect to DVSS.
Function
2 C bus mode)
2 C bus mode)
2
C bus mode)
2 C bus mode)
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