LG -D618 Service Manual page 152

< 2-1-3-1-1_MSM8226_DATA >
ZQ1 line is needed for 3-die LPDDR2 package
W/X is used 2die LPDDR (256M32D2 )
VREF_LPDDR2
6.3V
USB_HS2_SYSCLK is the first load on the CLK from PMIC
VREF_LDO_MPP_3
Make sure that CXO is the last load
Ground both P37 and K37 if WCN3620
6.3V
is used or if no WCN is used.
Rev_0.4
WTR0_PRXBB_I_N
WTR0_PRXBB_I_P
WTR0_PRXBB_Q_N
WTR0_PRXBB_Q_P
If not use, floating
1%
R2110 3.9K
WLAN_I_N
PIN WCN using BCM using
WLAN_I_P
3.9k DNI
R2110 WLAN_Q_N
IQ line connect to WCN GND WLAN_Q_P
WTR0_TXBB_I_N
WTR0_TXBB_I_P
WTR0_TXBB_Q_N
WTR0_TXBB_Q_P
WTR0_DAC_IREF
If DSDA, connect 3Pins to WTR2100
Refer to Ref. sch.
Near MSM
WTR0_GNSSBB_I_P
WTR0_GNSSBB_I_N
WTR0_GNSSBB_Q_P
C2102 DNI
VREG_L7_1V9
WTR0_GNSSBB_Q_N
LGE Internal Use Only
F21
USB_D_M USB_HS2_DM
E22
USB_D_P USB_HS2_DP
D23
USB_HS2_ID
TP2110
Rev_0.4
G24
USB_HS2_VBUS
TP2109
B25
HSIC_CAL
RESOUT_N
A22
R2100 200
USB_HS2_REXT
0.01
TOL=0.01
AM9
R2102 240 EBI0_CAL_REXT
TOL=0.01
AD1
R2104 240 EBI0_ZQ0
AY19
R2105 0 EBI0_ZQ1 PS_HOLD
05/30
Y39
VREF_DQ SDC1_CLK
AC2
VREF_CA SDC1_CMD
SDC1_DATA_0
AF33
EBI0_VREF_D0 SDC1_DATA_1
P33
EBI0_VREF_D1 SDC1_DATA_2
U2100
AM29
EBI0_VREF_D2 SDC1_DATA_3
J30
EBI0_VREF_D3 SDC1_DATA_4
AN10
EBI0_VREF_CA SDC1_DATA_5
SDC1_DATA_6
U6
VREF_APC_MPM SDC1_DATA_7
Rev_0.4
P37
WCN_XO QDSS_SDC2_TRCLK/SDC2_CLK
G20
USB_HS2_SYSCLK QDSS_SDC2_TRSYNC/SDC2_CMD
BB_CLK L6
CXO QDSS_SDC2_TRDATA_0/SDC2_DATA_0
B27
BB_CLK_EN
CXO_EN QDSS_SDC2_TRDATA_1/SDC2_DATA_1
B35
SLEEP_CLK
SLEEP_CLK QDSS_SDC2_TRDATA_2/SDC2_DATA_2
QDSS_SDC2_TRDATA_0/SDC2_DATA_3
AG2
BBRX_CH0_IM
AH1
BBRX_CH0_IP PMIC_SPMI_CLK
AG4
BBRX_CH0_QM PMIC_SPMI_DATA
AG6
BBRX_CH0_QP
AF5
BBRX_CH1_IM MIPI_CSI0_LN0_N
AF3
BBRX_CH1_IP MIPI_CSI0_LN0_P
AF1
BBRX_CH1_QM MIPI_CSI0_LN1_N/MIPI_CSI0_CLK_N
AE2
BBRX_CH1_QP MIPI_CSI0_LN1_P/MIPI_CSI0_CLK_P
MIPI_CSI0_LN2_N
U32
WLAN_REXT MIPI_CSI0_LN2_P
U34
WLAN_BB_IM MIPI_CSI0_LN3_N
V35
WLAN_BB_IP MIPI_CSI0_LN3_P
P35
WLAN_BB_QM MIPI_CSI0_LN4_N
R34
WLAN_BB_QP MIPI_CSI0_LN4_P
Near MSM
AB5
L2100 82n
TX_DAC0_IM MIPI_CSI1_LN0_N
L2101 82n AB3
TX_DAC0_IP MIPI_CSI1_LN0_P
L2102 82n Y1
TX_DAC0_QM MIPI_CSI1_LN1_N/MIPI_CSI1_CLK_N
L2103 82n W2
TX_DAC0_QP MIPI_CSI1_LN1_P/MIPI_CSI1__CLK_P
AA6
TX_DAC0_IREF
AD7
TX_DAC1_QM MIPI_DSI0_CLK_N
AC6
TX_DAC1_QP MIPI_DSI0_CLK_P
AE8
TX_DAC1_IREF MIPI_DSI0_LN0_N
MIPI_DSI0_LN0_P
AN4
GNSS_BB_IP MIPI_DSI0_LN1_N
AM3
GNSS_BB_IM MIPI_DSI0_LN1_P
AR4
GNSS_BB_QP MIPI_DSI0_LN2_N
AP3
GNSS_BB_QM MIPI_DSI0_LN2_P
MIPI_DSI0_LN3_N
MIPI_DSI0_LN3_P
Rev_0.4
AT31
SRST_N JTAG_SRST
AN34
TCK JTAG_TCK
AY35
TDI JTAG_TDI
AR32
JTAG_TDO
TDO
AW34
JTAG_TMS
TMS
AP33
TRST_N JTAG_TRST
D33
RESIN_N MSM_RESIN_N
E32
MSM_RESOUT_N
AU32
R2101 DNI
MODE_0 VREG_L6_1V8
AV31
R2103 DNI
MODE_1
An external pull for the MODE pins is not necessary.
C34
MSM_PS_HOLD
he only mode supported is MODE = 00, and both pins are internally pulled to GND by default.
Distance from the MSM clock pin to resistor should be < 5mm.
F1
R2106 0
eMMC_CLK
G6
eMMC_CMD
F3
EMMC_DATA_0
E2
EMMC_DATA_1
G4
EMMC_DATA_2
J2
EMMC_DATA_3
E4
EMMC_DATA_4
D1
EMMC_DATA_5
G2
EMMC_DATA_6
K1
EMMC_DATA_7
Rev_0.4
M3 Distance from the MSM clock pin to resistor should be < 5mm.
R2108 0
SDCARD_CLK
L4
SDCARD_CMD
M5
SDCARD_DATA_0
L2
SDCARD_DATA_1
M1
SDCARD_DATA_2
Near MSM
P1
SDCARD_DATA_3
G28
PMIC_SPMI_CLK
D27
PMIC_SPMI_DATA
AU26
MAIN_CAM0_MIPI_DATA0_N
AR26
MAIN_CAM0_MIPI_DATA0_P
AY25
MAIN_CAM0_MIPI_CLK_N
AW26
MAIN_CAM0_MIPI_CLK_P
AP23
MAIN_CAM0_MIPI_DATA1_N
AN24
MAIN_CAM0_MIPI_DATA1_P
AY23
MAIN_CAM0_MIPI_DATA2_N
AW22
MAIN_CAM0_MIPI_DATA2_P
AU22
MAIN_CAM0_MIPI_DATA3_N
AR22
MAIN_CAM0_MIPI_DATA3_P
AV27
VT_CAM_MIPI_DATA0_N
AT27
VT_CAM_MIPI_DATA0_P
AY27
VT_CAM_MIPI_CLK_N
AW28
VT_CAM_MIPI_CLK_P
AV17
LCD_MIPI_CLK_N
AT17
LCD_MIPI_CLK_P
AT21
LCD_MIPI_DATA0_N
AV21
LCD_MIPI_DATA0_P
AP19 <3-1-2-3-3_LPDDR2_POP_8Gbit_Micron>
LCD_MIPI_DATA1_N
AR20
LCD_MIPI_DATA1_P
AY15
AW14
AR16
AU16
- 152 -
< 9-3-1-1_JTAG > Rev_0.2
REF._W7_CCDS_V02
CN9300 BOM DNI
CN9300
1 14
JTAG_TCK
2 13
TP9301
1
3 12
JTAG_TDO
4 11
JTAG_TDI
5 10
JTAG_TMS
6 9
JTAG_TRST
7 8
VREG_L6_1V8
C2110
C2111
220n
220n
W7_X5_COMMON
U3100
1
Fiducial1
H9TKNNN8JDAPLR-NGH
Copyright © 2014 LG Electronics. Inc. All right reserved.
6. CIRCUIT DIAGRAM
MSM_UART_TX
MSM_UART_RX
JTAG_PS_HOLD
JTAG_SRST
Rev_0.3
Only for training and service purposes