Table of Contents
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1
3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM
3.1 BLOCK DIAGRAM
A
B
B
TUNER UNIT
ZIF TUNER
MAX2140ETH
F501
CN501
2
1
RFIN+
OUT1
5
XM SINGLE
IN
3
8
OUT2
ANTENNA
RFIN-
16
VOUTANT
5
IFOUT+
6
IFOUT-
F502
11
10
5
IFIN-
IN1
OUT1
C
1
10
6
IN2 OUT2
IFIN+
19
IF2IO+
17
IF2IO-
20
IF2II+
18
IF2II-
37
IF2QO+
39
IF2QO-
36
IF2QI+
38
IF2QI-
D
E
F
10
1
2
A
IC501
CN301
CN502
35
IF_Q+
QOUT-
8
8
34
IF_Q-
QOUT+
6
6
21
IF_I-
12
12
IOUT-
22
IF_I+
IOUT+
10
10
9
IF_AGC
AGCPWM
18
18
4
25
1
SYS_CLK
REFOUT
IN-
2
2
OUT
AMP
IC502
MAX999EUK
44
SDA
26
26
43
SCL
25
25
VDD_M3.3V
1
1
VCC_RF3.3V
15
15
17
VCC_ANT5.0V
17
24
XTAL
X501
GEX-P10XMT/XN/UC
2
3
MAIN UNIT
CAP
IC370
ST19AF08BR20QMAA
17
97
I2C_DATA
CAP_SDA_M
96
5
I2C_CLOCK
CAP_SCL_M
6
93
CAP_RST
RST
4
1
MCLK
CLKO
4
MCLK
15
INP1
14
INM1
18
INM2
17
INP2
37
AGC1
RAS,CAS,MDQM,MCSO
SDA
SDA
64
SDA
65
SCL
SCL
SCL
DIG_3.3V
RF_3.3V
ANT_5.0V
108 107 106 100 99 98 34 33
108 107 106 100 99 98 34 33
4
MCLK
15
INP1
14
INM1
18
INM2
17
INP2
64
SDA
SDA
65
SCL
SCL
NCSO,MWE,CLKON,MCKE
3
4
D/A CONVERTER
IC480
PCM1742KE
2
84
SD0
DATA
VoutL
1
83
SCKT
BCKIN
VoutR
82
3
LRCKT
LRCKIN
16
81
OCLK
MCLK
MASTER
IC300
STA850P
SDRAM
IC360
K4S280832F-TC75
D0-D7
MDQ0-7
DQ0-7
A0-A11
MADD0-11
A0-11
BS0,BS1
MBS0,1
BA0,1
RAS_,CAS_,
RAS,CAS,DQM
DQM,CS_,
MWE,CLKON,MCKE
CSO,WE,CLK,CKE
WE_,CLK,CKE
69
LSDPRX
RS232TX
66
INTR
CDEC_INTR
RESET_N
MRESET
VDD_3.3V
SLAVE
IC200
STA850P
SDRAM
IC260
K4S280832F-TC75
SD0-SD7
MDQ0-7
DQ0-7
SA0-SA11
MADD0-11
A0-11
SBS0,SBS1
BA0,1
MBS0,1
RAS_,CAS_,
RAS,CAS,MDQM,
SRAS,SCAS,SDQM
DQM,CS_,
SCSO,SWE,
WE_,CLK,CKE
SCLK,SCKE
4
LPF
IC490
NJM4558MD
2
7
1
LCH
IN-1
OUT1
6
8
7
RCH
IN-2
OUT2
15
DAC_EN
ML
14
DAC_CL
MC
13
DAC_DT
MD
11
X601
13
30
18
10
TX
TEST
3
POINT
RX
DAC_EN
57
100
DAC_CL
RESET
DAC_DT 99
IC603
S-80827CNNB-B8M
10
2
1
OUT
VDD
S602
RESET SW
59
RESET_N
MRESET
65
INTR
18
11
X602
13
SDA
93
95
SCL
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