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NAT-AMC-ZYNQUP-FMC
T
ECHNICAL
N.A.T. Gesellschaft für Netzwerk- und Automatisierungs-Technologie mbH
Konrad-Zuse-Platz 9 | 53227 Bonn, Germany | Phone: +49 228 965 864 - 0
sales@nateurope.com | www.nateurope.com
NAT-AMC-ZYNQUP-FMC
FMC C
ARRIER
D
N.A.T. G
ESIGNED BY
R
EFERENCE
HW R
EVISION
T
R
ECHNICAL
EFERENCE
B
OARD
H
MB
M
V1.1
ANUAL
1.
X
M
V1.1
ANUAL
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Table of Contents
Summary of Contents for N.A.T. NAT-AMC-ZYNQUP-FMC
- Page 1 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC-ZYNQUP-FMC FMC C ARRIER OARD N.A.T. G ESIGNED BY V1.1 ECHNICAL EFERENCE ANUAL HW R EVISION N.A.T. Gesellschaft für Netzwerk- und Automatisierungs-Technologie mbH Konrad-Zuse-Platz 9 | 53227 Bonn, Germany | Phone: +49 228 965 864 - 0...
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Page 2: Table Of Contents
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL ABLE OF ONTENTS PREFACE ....................6 1.1. Disclaimer ......................6 1.2. About This Document ..................7 INTRODUCTION ..................8 2.1. Applications ...................... 8 2.1.1............8 MAGE ROCESSING PPLICATIONS 2.1.2..............8 IRELESS PPLICATIONS 2.2. - Page 3 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3. Component-, Connector-, and Switch-Location ........22 5.3.1. J1: FMC C ..............23 ONNECTOR 5.3.2. J3: JTAG P ............39 ROGRAMMING EADER 5.3.3. J6: M ..............39 EMORY ONNECTOR 5.3.4. S1: AMC C ..............40 ONNECTOR 5.3.5.
- Page 4 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL IST OF ABLES Table 1 – Technical Data ................9 Table 2 – DDR4-Memory to FPGA Pin Assignment – Address CMD, REFCLK, RESET ..13 Table 3 – DDR4-Memory to FPGA Pin Assignment – DATA and Strobe ......14 Table 4 –...
- Page 5 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 31 – Document’s History ..............59 IST OF IGURES Figure 1 – Block Diagram ................12 Figure 2 – PLL and Clocking ................. 17 Figure 3 – IPMB-Interface ................18 Figure 4 – JTAG Architecture ................. 19 Figure 5 –...
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Page 6: Preface
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL REFACE 1.1. Disclaimer The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.), represents the current status of the product´s development. The documentation is updated on a regular basis. Any changes which might ensue, including those necessitated by updated specifications, are considered in the latest version of this documentation. -
Page 7: About This Document
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 1.2. About This Document This document is intended to give an overview on the NAT-AMC-ZYNQUP-FMC’s functional capabilities. Preface General information about this document Introduction Abstract on the NAT-AMC-ZYNQUP-FMC’s main functionality and application field Quick Start... -
Page 8: Introduction
EFERENCE ANUAL NTRODUCTION The NAT-AMC-ZYNQUP-FMC is a FMC carrier board in AMC form factor with integrated hardware elements, which make it the ideal platform for sophisticated wireless, machine vision, and SDR applications. The carrier board can be expanded be several FMC mezzanine modules, which offer the flexibility to address a broad range of applications. -
Page 9: Main Features
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 2.2. Main Features Table 1 – Technical Data Form Factor • Single-width, full-size or mid-size AMC • Width: 73.5 mm, Depth: 180.6 mm Processing Resources • Xilinx Zynq Ultrascale+ FPGA MPSoC; choice of ZU7EG, ZU11EG •... -
Page 10: Quick Start
Make sure the part to be installed / removed is hot-swap-capable, if you do not switch off the power. Ensure that the NAT-AMC-ZYNQUP-FMC is connected to the carrier board or to the µTCA backplane with the connector completely inserted. When operating the board in areas of strong electromagnetic radiation, ensure that the module is bolted to the front panel or rack, and shielded by closed housing. -
Page 11: Voltage Requirements
The NAT-AMC-ZYNQUP-FMC supports hot-swapping, which means that the board can be inserted or extracted during normal system operation without affecting other modules. Make sure to follow the procedure exactly to prevent the NAT-AMC-ZYNQUP-FMC or the system it is plugged into from damage! -
Page 12: Functional Description
ECHNICAL EFERENCE ANUAL UNCTIONAL ESCRIPTION The NAT-AMC-ZYNQUP-FMC can be divided into a number of functional blocks, which are described in the following paragraphs. The following figure gives an overview on the functional blocks. Figure 1 – Block Diagram Stratum III... -
Page 13: Programmable Logic (Fpga)
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 4.1.2. Programmable Logic (FPGA) 4.1.2.1. Programming The Programmable Logic of the ZYNQUP-SoC can be accessed via an onboard Xilinx Programming Module (JTAG-SMT3). It allows to program and debug the FPGA using a Micro- USB Cable, while it serves the same functionality as the Xilinx Platform Cable II programmer. -
Page 14: Table 3 - Ddr4-Memory To Fpga Pin Assignment - Data And Strobe
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 3 – DDR4-Memory to FPGA Pin Assignment – DATA and Strobe FPGA FPGA FPGA DDR4 Pin# Bank 65 DDR4 Pin# Bank 64 DDR4 Pin# Bank 63 Pin# Pin# Pin# DDR4_dqs_t[0] AW24 DDR4_dq[0] AU24 DDR4_dq[32]... -
Page 15: Table 4 - Memory Card: Ddr4-Memory To Fpga Pin Assignment - Fpga Bank 27
ECHNICAL EFERENCE ANUAL On request, the NAT-AMC-ZYNQUP-FMC can be equipped with several memory extension cards. Depending on the target application, different memory types can offer advantages; QDR4 and RLDRAM3 memory offers low latency random access, which is useful for applications requiring RAM look up tables (LUTs). -
Page 16: Table 5 - Memory Card: Ddr4-Memory To Fpga Pin Assignment - Fpga Bank 28
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 5 – Memory Card: DDR4-Memory to FPGA Pin Assignment – FPGA Bank 28 Address CMD, RESET, LED DATA and Strobe FPGA FPGA FPGA DDR4 Pin# DDR4 Pin# DDR4 Pin# Pin# Pin# Pin# DDR4_B28_adr[16] DDR4_B28_ba[0]... -
Page 17: Pll And Clocking
V1.1 ECHNICAL EFERENCE ANUAL 4.2. PLL and Clocking The NAT-AMC-ZYNQUP-FMC features a SI5347 PLL, which is user-configurable by the FPGA via I²C. Figure 2 – PLL and Clocking Bank 224 / AE11 FCLKA Bank 224 / AE12 Bank 66 / AT5... -
Page 18: Ipmb-Interface And I
EFERENCE ANUAL 4.3. IPMB-Interface and I C-Devices The NAT-AMC-ZYNQUP-FMC implements an IPMB interface consisting of an IPMI-µC (ATXMega128) and a couple of I C devices connected via I²C. The following figure shows the architecture in detail. Figure 3 – IPMB-Interface... -
Page 19: Jtag And Uart
ANUAL 4.4. JTAG and UART The NAT-AMC-ZYNQUP-FMC supports JTAG and serial UART via the front panel USB connector or the on-board JTAG programming header. Both interfaces can be used simultaneously and can be configured using on-board DIP switches. Configuration of the JTAG Master is possible via the JTAG MUX Switch; for detailed information on this switch, please refer to chapter 5.3.9 SW3: JTAG MUX. -
Page 20: Hardware
Front Panel and LEDs The front plate appearance and the labelling vary depending on the number and variant(s) of installed FMCs. The figure below shows the full-size version of the NAT-AMC-ZYNQUP-FMC carrier board. Figure 5 – Front Panel – Full Size Stat Table 6 –... -
Page 21: Amc Port Definition
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.2. AMC Port Definition Table 7 – AMC Port Definition Connector Region AMC Port # Signal CLK1/TCLKA Telecom Clock CLK2/TCLKB Telecom Clock Clocks CLK3/TCLKC Telecom Clock CLK4/TCLKD Telecom Clock CLK5/FCLKA Fabric Clock Common Options Custom... -
Page 22: Component-, Connector-, And Switch-Location
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3. Component-, Connector-, and Switch-Location Figure 6 – Location Diagram – Top Power Power Supply Supply eMMC QSPI Power Supply Figure 7 – Location Diagram – Bottom Power Atmel Power Supply µC Supply Temp EEPROM Progr. -
Page 23: J1: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3.1. J1: FMC Connector Connector J1 connects to an optional FMC mezzanine board Known limitations: • LA27, LA21, LA11, HA06 cannot be used for differential pair operation (on Rev 1.0) HB20, HB21 are not connected •... - Page 24 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL DP7_M2C_P LA05_N HA13_P LA08_P HA11_P DP7_M2C_N HA13_N HA12_P LA08_N LA07_P HA11_N HA10_P DP4_M2C_P LA10_P LA09_P HA12_N LA07_N HA10_N DP4_M2C_N LA10_N LA09_N HA16_P LA12_P HA14_P DP6_M2C_P HA16_N HA15_P LA12_N LA11_P HA14_N HA17_CC_P DP6_M2C_N LA13_P HA15_N LA11_N...
- Page 25 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL DP4_C2M_P FMC_GA0 FMC_JTAG_ HB19_N HB16_P LA31_N LA30_P HB15_N HB14_P TRSTn DP4_C2M_N 12POV FSIG_GA1 HB16_N LA30_N HB14_N DP6_C2M_P 3P3V HB21_P LA33_P HB18_P DP6_C2M_N 12POV HB21_N HB20_P LA33_N LA32_P HB18_N HB17_CC_P DP5_C2M_P 3P3V HB20_N LA32_N HB17_CC_N DP5_C2M_N...
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Page 26: Table 9 - J1A: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 9 – J1A: FMC Connector NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label DP1_M2C_P DP1_M2C_P 1V2_ MGTHRXP2_228 MGTA DP1_M2C_N DP1_M2C_N MGTHRXN2_228 DP2_M2C_P DP2_M2C_P 1V2_ MGTHRXP1_228 MGTA DP2_M2C_N DP2_M2C_N... -
Page 27: Table 10 - J1B: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label DP5_C2M_P DP5_C2M_P 1V2_ MGTHTXP2_227 MGTA DP5_C2M_N DP5_C2M_N MGTHTXN2_227 Table 10 – J1B: FMC Connector NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC... -
Page 28: Table 11 - J1C: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label DP7_C2M_P DP7_C2M_P 1V2_ MGTHTXP0_227 MGTA DP7_C2M_N DP7_C2M_N MGTHTXN0_227 DP6_C2M_P DP6_C2M_P 1V2_ MGTHTXP1_227 MGTA DP6_C2M_N DP6_C2M_N MGTHTXN1_227 RES0 FMC-RES0 Table 11 – J1C: FMC Connector... -
Page 29: Table 12 - J1D: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L12P_T1U_N10_GC LA18_P_CC LA18_CC_P VADJ IO_L12N_T1U_N11_GC LA18_N_CC LA18_CC_N LA27_P LA27_P IO_T2U_N12_68 VADJ LA27_N LA27_N IO_T3U_N12_68 I2C_SCL_3V3 PS-MIO10 I2C_SDA_3V3 PS_MIO11 FMC_GA0 12POV 12POV... - Page 30 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L17P_T2U_N8_AD1 LA09_P LA09_P 0P_68 VADJ IO_L17N_T2U_N9_AD1 LA09_N LA09_N 0N_68 LA13_P LA13_P IO_L24P_T3U_N10_67 VADJ LA13_N LA13_N IO_L24N_T3U_N11_67 IO_L11P_T1U_N8_GC_ LA17_P_CC LA17_CC_P VADJ IO_L11N_T1U_N9_GC_...
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Page 31: Table 13 - J1E: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 13 – J1E: FMC Connector NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L13P_T2L_N0_GC_ HA01_P_CC HA01_CC_P QBC_67 VADJ IO_L13N_T2L_N1_GC_ HA01_N_CC HA01_CC_N QBC_67 IO_L10P_T1U_N6_QBC HA05_P HA05_P _AD4P_67 VADJ IO_L10N_T1U_N7_QB... -
Page 32: Table 14 - J1F: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label HB21_P HB21_P HB21_N HB21_N VADJ Vadj Table 14 – J1F: FMC Connector NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin#... -
Page 33: Table 15 - J1G: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label HB04_P HB04_P IO_L11P_AD9P_88 VIO_B _M2C HB04_N HB04_N IO_L11N_AD9N_88 HB08_P HB08_P VIO_B IO_L10P_AD2P_87 _M2C HB08_N HB08_N IO_L10N_AD2N_87 HB12_P HB12_P IO_L3P_AD9P_87 VIO_B HB12_N... - Page 34 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L7N_T1L_N1_QBC_ LA12_N LA12_N AD13N_68 IO_L10P_T1U_N6_QBC LA16_P LA16_P _AD4P_68 VADJ IO_L10N_T1U_N7_QB LA16_N LA16_N C_AD4N_68 IO_L21P_T3L_N4_AD8 LA20_P LA20_P P_67 VADJ IO_L21N_T3L_N5_AD8 LA20_N LA20_N...
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Page 35: Table 16 - J1H: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 16 – J1H: FMC Connector NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label VREF_A_M2C VREF_A_M2C VADJ VREF_66 AK11 PRSNT_M2C_L PRSNT_M2C_L CLK0_M2C_P CLK0_M2C_P CLK0_M2C_N CLK0_M2C_N IO_L4P_T0U_N6_DBC_ LA02_P LA02_P AD7P_68... -
Page 36: Table 17 - J1I: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L20P_T3L_N2_AD1 LA30_P LA30_P P_68 VADJ IO_L20N_T3L_N3_AD1 LA30_N LA30_N N_68 IO_L21P_T3L_N4_AD8 LA32_P LA32_P P_68 VADJ IO_L21N_T3L_N5_AD8 LA32_N LA32_N N_68 VADJ VADJ Table 17 – J1I: FMC Connector... -
Page 37: Table 18 - J1J: Fmc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L9P_T1L_N4_AD12 HA21_P HA21_P P_66 VADJ IO_L9N_T1L_N5_AD12 HA21_N HA21_N N_66 HB01_P HB01_P VIO_B IO_L12P_AD8P_88 _M2C HB01_N HB01_N IO_L12N_AD8N_88 HB07_P HB07_P IO_L12P_AD0P_87 VIO_B... - Page 38 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA FMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label IO_L12P_T1U_N10_GC HA17_P_CC HA17_CC_P VADJ IO_L12N_T1U_N11_GC HA17_N_CC HA17_CC_N IO_L9P_T1L_N4_AD12 HA21_P HA21_P P_66 VADJ IO_L8N_T1L_N3_AD5N HA21_N HA21_N IO_L6P_T0U_N10_AD6 HA23_P HA23_P P_66 VADJ IO_L6N_T0U_N11_AD6...
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Page 39: J3: Jtag Programming Header
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3.2. J3: JTAG Programming Header Connector J3 offers a JTAG programming interface. Figure 8 – J3: JTAG Programming Header Table 19 – J3: JTGA Programming Header – Pin Assignment Pin # Signal Signal Pin #... -
Page 40: S1: Amc Connector
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3.4. S1: AMC Connector Figure 9 – S1: AMC-Connector (top view) Table 20 – S1A: AMC-Connector Top – Pin-Assignment NAT-AMC- FPGA FPGA FPGA AMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label +12V_PP PS1# /AMC_PS1 +3.3V_MP... - Page 41 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA AMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label TX1+ PORT1-Tx_P 1V2_ MGTHTXP0_225 MGTA PORT1-Tx_N TX1- MGTHTXN0_225 RX1+ PORT1-Rx_P 1V2_ MGTHRXP0_225 MGTA PORT1-Rx_N RX1- MGTHRXN0_225 AMC_GA2 +12V_PP PORT2-Tx_P IO_L22P_T3U_N6_DBC TX2+...
- Page 42 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA AMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label AMC_SCL +12V_PP TX6+ PORT6-Tx_P 1V2_ MGTHTXP1_224 MGTA PORT6-Tx_N TX6- MGTHTXN1_224 RX6+ PORT6-Rx_P 1V2_ MGTHRXP1_224 MGTA PORT6-Rx_N RX6- MGTHRXN1_224 TX7+ PORT7-Tx_P 1V2_...
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Page 43: Table 21 - S1B: Amc-Connector Bottom - Pin-Assignment
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Table 21 – S1B: AMC-Connector Bottom – Pin-Assignment NAT-AMC- FPGA FPGA FPGA AMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label RX8- PORT8-Rx_N 1V2_ MGTHRXN3_223 MGTA PORT8-Rx_P RX8+ MGTHRXP3_223 TX8- PORT8-Tx_N 1V2_ MGTHTXN3_223 MGTA... - Page 44 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NAT-AMC- FPGA FPGA FPGA AMC Label ZYNQUP-FMC VCCO Pin# Bank Pin Name Pin# Label TX13- PORT13-Tx_N 1V2_ MGTHTXN3_225 MGTA PORT13-Tx_P TX13+ MGTHTXP3_225 RX14- PORT14-Rx_N 1V2_ MGTHRXN0_226 MGTA PORT14-Rx_P RX14+ MGTHRXP0_226 TX14- PORT14-Tx_N 1V2_ MGTHTXN0_226 MGTA...
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Page 45: S2: Microsd-Card Slot
AMC_TCK AMC_TMS TRST# AMC_TDO AMC_TDI 5.3.5. S2: MicroSD-Card Slot The NAT-AMC-ZYNQUP-FMC features a MicroSD-Card slot at the front panel. Figure 10 – S2: MicroSD-Card Slot Table 22 – S2: MicroSD-Card Slot – Pin Assignment Pin # Signal Signal Pin #... -
Page 46: S3: Usb-/ Uart Connector
ECHNICAL EFERENCE ANUAL 5.3.6. S3: USB-/ UART Connector The NAT-AMC-ZYNQUP-FMC features an USB-/ UART interface via a Micro-USB connector at the front panel. Figure 11 – S3: USB-/ UART Connector Table 23 – S3: USB-/ UART Connector – Pin Assignment... -
Page 47: Sw1: Hot Swap Switch
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3.7. SW1: Hot Swap Switch Switch SW1 is used to support Hot-Swapping of the module. It conforms to PICMG AMC.0. 5.3.8. SW2: FMC Configuration Switch The tables below provide information on the operating parameters and configuration options of SW2. -
Page 48: Sw3: Jtag Mux Switch
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3.9. SW3: JTAG MUX Switch The tables below provide information on the operating parameters and configuration options of SW3. Figure 13 – SW3: JTAG MUX Switch Table 26 – SW3 – Operating Parameters Switch #... -
Page 49: Sw4 : Boot Mode Select Switch
The tables below provide information on the operating parameters and configuration options of SW4. Figure 14 – SW4: Boot Mode Select Switch Switch SW4 determines the boot mode of the NAT-AMC-ZYNQUP-FMC according to the following figure. Figure 15 – SW4: Boot Mode Select... -
Page 50: Sw6: Uart Mux
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 5.3.11. SW6: UART MUX The tables below provide information on the operating parameters and configuration options of SW6. Figure 16 – SW6: UART MUX Table 28 – SW6 – Operating Parameters Switch # Function SW6-1... -
Page 51: Fmc Operation
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL FMC O PERATION 6.1. Front panel Depending on the used FMC the front panel metalwork may not fit and needs to be reworked. This is needed in case FMC with 8.5 mm stacking height are used that do not fit into the standard front panel cut out which is made for 100 mm stacking height FMCs. -
Page 52: Fmc Eeprom Wizard
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Figure 18 – Installing FMC Module Part 2 6.4. FMC EEPROM Wizard Per default, the carrier will try to parse the FMC FRU records from the modules EEPROM contents to set the carrier’s power supply and clock direction. In case there is an FMC without records, there are two options: Generate and program the records with the carrier. - Page 53 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL The MMC has to be rebooted with triggering the HS-Handle. The console output should output the following line: Press any key to generate FMC FRU file ... 5.0 Within five seconds time press any key to enter the FMC programming mode. This mode is guided and will lead through the steps to program the FMC records.
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Page 54: Known Issues
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL NOWN SSUES PCB V1.0 has the following known issues: LA27, LA21, LA11, HA06 cannot be used for differential pair operation • Clock Direction of CLK2_BIDIR is fixed at C2M • HA14, HA10: P-/N-Labelling at FPGA is switched •... -
Page 55: Specifications And Compliances
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL PECIFICATIONS AND OMPLIANCES 8.1. Internal Reference Documentation For further documentation on NAT-AMC-ZYNQUP-VISION and NAT-AMC- • ZYNQUP-SDR4/8, please contact N.A.T. 8.2. External Reference Documentation Atmel ATxmega128 µC Product Datasheet, Rev A, 08/2018 • Micron MT40A512M16LY-062 DDR4 SDRAM Datasheet, Rev. P, 04/2019 •... -
Page 56: Compliance To Weee Directive
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL RoHS directive if it does not belong to one of the groups of products exempted from the RoHS directive. Although many of hardware products of N.A.T. are exempted from the RoHS directive it is a declared policy of N.A.T. -
Page 57: Compliance To Reach
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL 8.8. Compliance to REACH The REACH EU regulation Regulation (EC) No 1907/2006) is known to N.A.T. GmbH. N.A.T. did not receive information from their European suppliers of substances of very high concern of the ECHA candidate list. Article 7(2) of REACH is notable as no substances are intentionally being released by NAT products and as no hazardous substances are contained. - Page 58 NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL Abbreviation Description Serial Attached SCSI SATA Serial Advanced Technology Attachment Software Defined Radio System on a Chip SRIO Serial Rapid I/O TCKL Telecom Clock UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus - 58 - PECIFICATIONS AND...
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Page 59: Document's History
NAT-AMC-ZYNQUP-FMC V1.1 ECHNICAL EFERENCE ANUAL ’ OCUMENT ISTORY Table 31 – Document’s History Date Description Author 12.12.2019 initial release • 11.02.2020 Added title foto • 22.04.2020 Added FMC-Signal routing information • Added PLL-/Clocking information • 29.04.2020 Minor changes • 20.01.2021 Updated Block Diagram in chapter 4 •...