Table of Contents
Advertisement
4.10 MAIN(2D DIGITAL) SCHEMATIC DIAGRAM
5
4
3
TO S_SUB
I2C_DATA_A/V
I2C_CLK_A/V
2
CTL5
C_FROM_DIGI
GND
Y_FROM_DIGI
V/Y_TO_DIGI
SW5V
C_TO_DIGI
GND
Fsc
1
A
0
3 MAIN[2D DIGITAL]
LC1201
100µ
C1246
47
/6.3
C1203
C1204
OPEN
100p
R1203
R1204
KILLER_DET
R1205
C1209
R1206
560
L1201
OPEN
: USED
: NOT USED
#DIFFERENCE TABLE 1
MODEL
R1229
US, UM, UC
JP
B
Q1201
2SC1317/RS/
R1201
R1202
120
100
C1201
D1201
47
RD3.9ES/B2
/6.3
#
R1229
2.2k
1k
1k
1k
OPEN
C1210
OPEN
L1202
L1203
100µ
D/A LEVEL ADJ
R1210
39k
0.5%
R1223
SHORT
L1204
100µ
C1220
47
/6.3
R1212
OPEN
C1243
L1205
0.01
SHORT
B1201
Q1202
R1213
C1222
OPEN
OPEN
OPEN
R1215
OPEN
C1244
L1206
4.7
/25
SHORT
B1202
C1226
Q1203
R1216
C1225
OPEN
OPEN
OPEN
R1231
C
D
C1211
47
/6.3
R12
5.6
330µ
IC1201
JCP8057
C1215
47
/6.3
IIC_
IIC_
RE
CM
VS
C1217
0.1
VD
C1218
0.1
VR
R1211
CO
18k
0.5%
IOB
C1219
1
R1221
CO
OPEN
YO
R1214
R1217
75
68
0.5%
C1208
OPEN
Q1207
C1223
OPEN
C12
47p
OPEN
100
4-21
Advertisement
Table of Contents
