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6 - 1
Main Board
TABLE OF CONTENTS
Circuit Diagram................................................................................................................ 6-2
PCB Layout Top View ..................................................................................................... 6-
PCB Layout Bottom View .............................................................................................. 6-
6 - 1
STM8S105XX DIAGRAM
Reset block
Clock controller
Reset
Reset
Detector
POR
BOR
Clock to peripherals and core
STM8 core
Single wire
Debug/SWIM
debug interf.
Master/slave
autosynchro
UART2
LIN master
SPI emul.
2
400 Kbit/s
I
C
8 Mbit/s
SPI
16-bit advanced control
Up to 10 channels
ADC1
1/2/4 kHz
Beeper
beep
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
Window WDG
Independent WDG
Up to 32 Kbytes
program Flash
1 Kbytes
data EEPROM
Up to 2 Kbytes
RAM
Boot ROM
Up to
4 CAPCOM
channels +3
timer (TIM1)
complementary
outputs
Up to
16-bit general purpose
5 CAPCOM
timers (TIM2, TIM3)
channels
8-bit basic timer
(TIM4)
AWU timer
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