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RH-44
Troubleshooting — BB
DBUSClk Interface
A 9.6 MHz clock signal is used for DBUS, which is used by the DSP to transfer data
between UEM and UPP. (See following figure.)
The system clock is stopped during sleep mode by disabling the VCTCXO power supply
(VR3) from the UEM regulator output by turning off the controlled output signal SleepX
from UPP.
SLEEPClk (Digital)
The UEM provides a 32kHz sleep clock for internal use and to UPP, where it is used for
Page 16
Figure 9: Cbus data transfer
Figure 10: Dbus data transfer
Nokia Corporation
CCS Technical Documentation
Confidential
Issue 1 04/2003
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Table of Contents
Troubleshooting
