User I/O - ADT ADZBT1HP Hardware User Manual

ADZBT1HP Hardware User Manual

3.9 User I/O

User I/O
J1 67Pin
J2 66Pin
Pin
J1
J1
Pin Pin
1
3
5
7
9
11 A10
13 A11
15
17 B9
19 C18
21
23 F12
25 C15
27 D15
J1 67Pin J2 66Pin
FX10A-100P/10-SV1 Hirose
FX10A-100P/10-SV1 Hirose
FPGA
Port
+3.3V
+3.3V
+3.3V
+3.3V
GND
PS_MIO37 (OTG_data5)
PS_MIO36 (OTG_clk)
GND
PS_MIO51 (ETH PHY Reset)
PS_MIO39 (OTG_data7)
GND
PS_MIO35 (OTG_data3)
PS_MIO30 (OTG stp)
PS_MIO33 (OTG_data1)
J1
Pin Pin
2
4
6
8
10
12 A12
14 B13
16
18 A14
20 C16
22
24 E16
26 C13
28
12/17
FPGA
Port
+3.3V
+3.3V
+3.3V
+3.3V
GND
PS_MIO34 (OTG_data2)
PS_MIO50 (ETH Interrupt)
GND
PS_MIO32 (OTG_data0)
PS_MIO20 (OTG_data4)
GND
PS_MIO31 (OTG nxt)
PS_MIO29 (OTG dir)
GND