Philips 40PFL4901/F7 Service Manual page 57

Digital Main 7 Schematic Diagram [TYPE A]
1 NOTE:
The order of pins shown in this diagram is different from that of actual IC3102.
IC3102 is divided into five and shown as IC3102 (1/5) ~ IC3102 (5/5) in this Digital Main Schematic Diagram Section.
DIGITAL MAIN CBA UNIT
4
C9006
1000P
JK9301
ANT-IN
C9001 C9002 C9018
L9007
330P 120P 82P
5.6nH
L9001 C9014 C9003 C9015
0.27uH VARISTOR 180P 2P
3
L9002
0.22uH
2
1
AK
C9011 C9012
X9001
1000P 1000P
24MHz
1 4
2 3
18 17 16 15 14 13
L9003
0.27uH
19 RF-REF NU 12
C9022 C9021
C9004 L9004
1P 1P
150P 0.27uH
20 RF-IP 11
OUTPUT
I/F
C9017
1P
21 GND 10
C9005
150P
DSP
22 PGA ADC VCC 9
/FILTER
L9005 C9010 C9023
0.27uH 1000P 1P
23 GND GND 8
RF
L9006
AGC
0.27uH 24 NU VDDL 7
C9008 C9009
1000P 1
IC9001
SI2151 1 2 3 4 5 6
(SILICON TUNER)
C9019 C9007
OPEN R9001 R9003 0.1
100 1K
R9002
C9020
100
OPEN
C3906
OPEN
AL AM
C9013 C9016
0.1 1
R9005
100
R9004
100
C3927 C3926
33P 33P
C3160
C3165
R3147 OPEN
0.1
33
C3156 L3105
C3164
R3146 OPEN OPEN
0.1
33
C3155
OPEN
R3207
L3913
47
2.2uH
D3901 D3902 D3903
C3905 C3908 C3909
MM5Z5V6B MM5Z5V6B MM5Z5V6B
10 33P 33P
R3936
C3910 D3904 C3161
100
0.1 MM5Z5V6B 0.022
AN
10-9
CN9001 (NO CONNECTION)
1 +3.3V
2 GND
3 DIF(+)
4 DIF(-)
CN9002 (NO CONNECTION)
1 IF-AGC
2 SCL
3 SDA
4 GND
*1
IC3102(5/5)
MSD93F0JM4-3-002J
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
C3154
R3162
0.1
51
49
DEMODULATOR
/MPEG
C3153
R3161
0.1 DECODER
51
48
TO DIGITAL TO DIGITAL
MAIN 4 MAIN 4
IC3102(2/5) IC3102(2/5)
R3206
47
R3938
4.7K
R3937
4.7K
87 TU-SCL
88 TU-SDA
R3117
0
47 IF-AGC
R3160
10K
L3102
BEAD
C3159
1
CONTINUE
DIGITAL 6
P-ON+3.3V
AO AP
PL15.01ASCD7