Transm Itter System; Pll Synthesizer Circuit - Alinco DJ-493 Service Manual

5. Squelch Circuit

2) Transm itter System

1. Modulator Circuit
2. Power Amplifier Circuit
3. APC Circuit
3)

PLL Synthesizer Circuit

1. PLL
2. Reference Frequency Circuit
4
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The signal except for the noise component in AF signal of 104 is cut by the
active filter inside 1C. The noise component is amplified and rectified, then
converted to the DC voltage to output from pin13 of IC4. The voltage is led to
pin 2 of CPU and compared with the setting voltage. The squelch will open if
the input voltage is lower than the setting voltage.
The audio signal is converted to an electric signal in either the internal or
external microphone, and input to the microphone amplifier (IC8). IC8 con­
sists of two operational amplifiers; one amplifier (pins 5, 6, and 7) is composed
of pre-emphasis and IDC circuits and the other (pins 1, 2, and 3) is composed
of a splatter filter. The maximum frequency deviation is obtained by VR1 and
input to the cathode of the varicap of the VCO, to change the electric capacity
in the oscillation circuit. This produces the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the pre-drive IC
(IC1) and drive amplifier (04), and input to the final amplifier (02). The signal
is then amplified by the final amplifier (02) and led to the antenna switch (D2)
and low-pass filter (L5, L 3 ,12, C24, C11, 010, and C9), where unwanted high
harmonic waves are reduced as needed, and the resulting signal is supplied
to the antenna.
Part of the transmission power from the low-pass filter is detected by D7, con­
verted to DC, and then amplified by a differential amplifier. The output voltage
controls the bias voitage from the source of 0 2 and 0 4 to maintain the trans­
mission power constant.
The dividing ratio is obtained by sending data from the CPU (IC9) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC2). The oscillated signal from the
VCO is amplified by the buffer (05, 037) and input to pin 6 of IC2. Each
programmable divider in IC2 divides the frequency of the input signal by N
according to the frequency data, to generate a comparison frequency of 5 or
6.25kHz.
The reference frequency appropriate for the channel steps is obtained by di­
viding the 21,25MHz reference oscillation (X1) by 4250 or 3400, according to
the data from the CPU (IC9). When the resulting frequency is 5kHz, channel
steps of 5, 10, 15, 20, 25, 30, and 50kHz are used. When it is 6.25kHz, the
12.5kHz channel step is used.