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National Instruments myRIO-1950 Instructions Manual
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National Instruments myRIO-1950 Instructions Manual

National Instruments myRIO-1950 Instructions Manual

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myRIO-1950 JTAG Instructions
This document is intended to give instructions on how to use the myRIO-1950 JTAG port for
lead users. This is not intended for the general public and should be distributed with caution.
Using the JTAG port may cause permanent damage to the myRIO-1950 if improperly used.
1.0 General JTAG specifications
Logic Level: 1.8V
Max JTAG Frequency: 10Mhz
Devices in JTAG Chain
Number of JTAG Instruction Registers:
1
NOTE that the JTAG pins are ESD sensitive. Additionally they may be damaged if overvoltage
above 1.8V. Be sure to attach the VREF pin of the JTAG programmer properly. Do not force the
JTAG programmer to use any voltage other than 1.8V on its IO.
2
CAUTION: The CPLD is not intended for customer access over JTAG. If you modify the CPLD your
myRIO-1950 will no longer function properly. Do not attempt to program the CPLD.
1
2
:
1st) Zynq PS (Arm processor)
2nd) Zynq PL (FPGA Fabric)
3rd) LCMXO2-640 CPLD
Zynq PS = 4
Zynq PL = 6
CPLD
= 8
2

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Summary of Contents for National Instruments myRIO-1950

  • Page 1 JTAG Instructions This document is intended to give instructions on how to use the myRIO-1950 JTAG port for lead users. This is not intended for the general public and should be distributed with caution. Using the JTAG port may cause permanent damage to the myRIO-1950 if improperly used.

  • Page 2: Physical Characteristics

    2.0 Physical Characteristics When accessing JTAG on the myRIO-1950 be sure that header J5 is populated. If it is not then populate this header with a through hole 2x3 0.1" spaced standard header. Note that Pin 1 is labeled with a 1 and pin 6 is labeled with a 6.
  • Page 3 The following figure shows the JTAG header's pinnout. Figure 2: Pinnout of JTAG header...

  • Page 4: General Instructions

    3.0 General Instructions: 1) Attach the JTAG programmer to the JTAG header, connecting TDO to TDO, TCK to TCK, TDI to TDI, TMS to TMS, GND to GND, and 1.8V to VREF. 2) Since this JTAG chain has multiple devices the JTAG software usually needs to know about all the devices in the chain to operate properly.
  • Page 5 4.0 FPGA Pinnout and UCF File: The following is a snapshot of a UCF file that defines the pinnout of the FPGA portion of the Zynq. Note that some of these pins are a part of SPI ports and an I2C port that goes to the onboard Dacs, ADCs, and accelerometer.
  • Page 6 NET "aMxpAdio8" LOC = Y16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output NET "aMxpAdio9" LOC = P14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output NET "aMxpAdio10" LOC = P18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; #input/output NET "aMxpAdio11"...
  • Page 7 NET "aAoMxpSpiMosi_n" OFFSET = OUT 20 ns AFTER "Clk40"; #Accelerometer I2c Timing NET "aAccelSda" OFFSET = IN 5 ns VALID 10 ns BEFORE "Clk40"; NET "aAccelScl" OFFSET = OUT 20 ns AFTER "Clk40"; #Accelerometer I2c Parameter NET "aAccelSda" OFFSET = OUT 20 ns AFTER "Clk40"; #Accelerometer I2c Parameter ################################################################################## ################################################################################## Special Pinnout instructions:...