LG 37LH250H Service Manual page 35

FPGA POWER
+3.3V
3.3V_Proidiom
L1227
010:T25;010:AJ26
3.3V_Proidiom +VCCINT_1.5V
MLB-201209-0120P-N2
MLB-201209-0120P-N2
L1228
C2177
100uF
16V
RESET
3.3V_Proidiom
OPT
1N4148W
R2390 D1250
10K 008:AP22;005:AM26
OPT
010:Q17 R2393
VSB_RESET
100
FPGA_RESET
OPT
C2179
OPT
R2394
008:AB21
1uF
100
25V
SYS_RESET
IC1210 3.3V_Proidiom
MAX809RTR
RESET VCC
2 3
1
C2255
GND
1uF
25V
OPT
27MHz
3.3V_Proidiom
X1006
27MHz
6 1
C2178 5 2
C2176
0.1uF
10uF
16V
16V 4 3
R2387 22
010:Q17 DE_H_SYSCLK
I2C
3.3V_Proidiom
SCL_SUB/AMP +5V_GENERAL
008:AI4;003:E6
0 R2446
D
MSCL_3.3V
B
0 R2447
FE_DEMOD_SCL S G
Q1114
008:AI5;005:AN21
BSS83
C2180
3.3V_Proidiom 0.1uF
16V
SDA_SUB/AMP OPT
008:AI4;003:E6
0
R2448
D
MSDA_3.3V
B
0
R2449
FE_DEMOD_SDA S G
Q1115
008:AI5;005:AN21
BSS83
C2181
0.1uF
16V
OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FPGA
3.3V_Proidiom
005:AN19 TS_CLK
TS_VALID
005:AN19
005:AN19 TS_SYNC
TS_0
005:AF17 TS_0
TS_1
TS_1
005:AF17
TS_2
005:AF17 TS_2
TS_3
TS_3
005:AF17
TS_4
005:AF16 TS_4
TS_5
005:AF16 TS_5
TS_6
005:AF16 TS_6
TS_7
005:AF16 TS_7
10K
R2422
GND
3.3V_Proidiom
3.3V_Proidiom
R2406 10K
OPT
DE_H_SYSCLK
010:C12
010:B19 FPGA_RESET
R2415 22
MSCL_3.3V
R2416 22
MSDA_3.3V
R2417 22
R2412 10K
R2413 10K
R2414 10K
3.3V_Proidiom
R240910K
R2408 10K
1K
R2402
1K
R2403
1K
R2404
R2405 OPT
GND
R2401
R2399
0
0
+VCCINT_1.5V
MLB-201209-0120P-N2
MLB-201209-0120P-N2 L1231
L1230
C2189
C2186
3.3uF
3.3uF
16V 16V 16V 16V 50V
50V
R2424 0
CLK1
H1
IO2_29/TP_SOP
B8
IO2_21/TP_VALID
B9
IO2_17/TP_ERR
B10
IO2_41/TP_DATA[7]
C5
IO2_36/TP_DATA[6]
C6
IO2_31/TP_DATA[5]
C7
IO2_25/TP_DATA[4]
C8
IO2_23/TP_DATA[3]
C9
IO2_18/TP_DATA[2]
C10
IO2_14/TP_DATA[1]
C11
IO2_8/TP_DATA[0]
C12
IO1_29
M1
IO1_2
C3
IO1_3
C2
IO1_4
B1
IO1_5
G5
IO1_6
F4
IO1_7
D3
IO1_8
E4
IC1209
0
IO1_9
F5
IO1_10
R2420 E3
IO1_11
D2
IO1_12 LGDT1129
E2
CLK0
G1
IO2_48/RESET
B2
IO3_37/I2C_SCK
D14
IO3_34/I2C_SDA
E14
DCLK
K4
CONF_DONE
K13
NCONFIG
H3
NCE
J4
DATA0
H2
IO1_21SO
G4
IO1_22/ASDO
K3
NCEO
H4
NSTATUS
J13
MSEL0
J3
MSEL1
J2
TCK
J14
TDO
H15
TMS
J15
TDI
H14
IO1_1/INIT_DONE
D4
IO1_13
D1
IO1_14
R2421 F3
0 IO1_15
G3
IO1_16
F2
IO1_17
E1
IO1_18
G2
IO1_19
F1
IO1_20
H5
IO1_23
J1
IO1_24
K2
IO1_25
L3
IO1_26
R2419 K1
0
IO1_27
L1
IO1_28
L2
IO1_30
N1
IO1_31
M2
IO1_32
N2
IO1_33
M3
R2423
IO1_34
L5
IO1_35
0 M4
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
IO4_34/CH_CLK
R11
IO4_20/CH_VALID
R8
IO4_26/CH_SOP
R9
IO4_30/CH_ERR
R10
IO4_8/CH_DATA[0]
P5
IO4_13/CH_DATA[1]
P6
IO4_18/CH_DATA[2]
P7
IO4_24/CH_DATA[3]
P8
IO4_28/CH-DATA[4]
P9
IO4_33/CH_DATA[5]
P10
IO4_35/CH_DATA[6]
P11
IO4_41/CH_DATA[7]
P12
IO2_34
E7
IO2_33
A6
IO2_32
B7
IO2_43
A4
IO2_30
D7
IO2_28
A8
IO2_27
E8
IO2_26
D8
IO2_44
B4
IO2_24
E10
IO2_45
C4
IO2_22
D9
IO2_20
A9
IO2_19
D10
IO2_16
A11
IO2_15
B11
IO2_46
B3
IO2_13
D11
IO2_12
D12
IO2_11
E9
IO2_10
E11
IO2_9
E12
IO2_47
A2
IO2_7
B12
IO2_6
A13
IO2_5
B13
IO2_4
C13
IO2_3
B14
IO2_2
A15
IO2_1
B15
IO3_43
D13
IO3_42
C14
IO3_41
C15
IO3_40
B16
IO3_39
G12
IO3_38
H13
IO3_36
E13
IO3_35
F12
IO3_33
D15
IO3_32
D16
IO3_31
E15
IO3_30
E16
IO3_29
F15
IO3_28
F13
IO3_27
F14
IO3_26
F16
IO3_25
G15
IO3_24
G13
IO3_23
G14
IO3_22
H12
CLK2
G16
CLK3
H16
R2431 0
R2426
0
R2425 0
37LH250H
FPGA
3.3V_Proidiom
+VCCINT_1.5V
OPT
C2219
62pF
50V
008:AP25
R2441 100
PM_TS_CLK
R2442 100 008:AP25
PM_TS_VALID
R2443 100 008:AP25
PM_TS_SYNC
R2444 100
PM_TS[0]
PM_TS[1]
PM_TS[2]
PM_TS[3]
PM_TS[4]
PM_TS[5]
PM_TS[6]
PM_TS[7]
008:AP27
PM_TS[0-7]
INNER LAYER PATERN
R2435 0
R2436 0
09.05.19
10 14