Clock Setting - NEC 78K0S/K 1+ Series Application Note

Led lighting switch control sample program (initial settings)
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4.5

Clock Setting

(1) Clock frequency setting
The CPU clock frequency (f
generated by dividing the frequency of the system clock set with the option byte.
The PPCC and PCC registers are used to select the CPU clock frequency (f
supplied to peripheral hardware (f
In this sample program, the PPCC and PCC registers are set as described in
that f
= f
= 2 MHz.
CPU
XP
Figure 4-3. Formats of Processor Clock Control Register (PCC) and Preprocessor Clock Control Register
PPCC
0
0
0
PCC
0
0
0
Cautions 1. Bits 2 to 7 of PPCC and bits 0 and 2 to 7 of PCC must be set to 0.
2. The clock frequency range that can be used varies, depending on the power supply voltage.
Resonator
Ceramic
resonator, crystal
resonator,
external clock
High-speed
internal oscillator
Note Use standard products and (A)-grade products within a voltage range of 2.2 to 5.5 V, since the detection
voltage (V
POC
Use (A2)-grade products within a voltage range of 2.26 to 5.5 V, since the detection voltage (V
power-on-clear (POC) circuit is 2.26 V (MAX.).
Remark
f
: System clock frequency
X
The system clock to be used is set using the option byte. For details, refer to
CHAPTER 4 SETTING METHODS
) and the frequency of the clock supplied to peripheral hardware (f
CPU
).
XP
0
0
0
PPCC1 PPCC0
0
0
0
PCC1
Conditions
125 kHz ≤ f
4.0 to 5.5 V
125 kHz ≤ f
3.0 to 4.0 V
125 kHz ≤ f
2.7 to 3.0 V
125 kHz ≤ f
Note
2.0 to 2.7 V
500 kHz (TYP.) ≤ f
4.0 to 5.5 V
500 kHz (TYP.) ≤ f
2.7 to 4.0 V
500 kHz (TYP.) ≤ f
Note
2.0 to 2.7 V
) of the power-on-clear (POC) circuit is 2.1 V ±0.1 V.
Application Note U18752EJ2V0AN
(PPCC)
0
PPCC1 PPCC0
PCC1
0
0
0
0
0
1
0
1
1
0
1
0
Other than the above
CPU Clock Frequency (f
)
CPU
≤ 10 MHz
CPU
≤ 6 MHz
CPU
≤ 5 MHz
CPU
≤ 2 MHz
CPU
≤ 8 MHz (TYP.)
CPU
≤ 4 MHz (TYP.)
CPU
≤ 2 MHz (TYP.)
CPU
) and the frequency of the clock
CPU
[ Example
1], mentioned later, so
2 7 H
CPU Clock
Peripheral Hardware
Frequency
Clock Frequency
(f
)
(f
)
CPU
XP
0
f
f
X
X
1
f
/4
f
X
X
0
f
/2
f
/2
X
X
1
f
/8
f
/2
X
X
0
f
/4
f
/4
X
X
1
f
/16
f
/4
X
X
Setting prohibited
Peripheral Hardware Clock
Frequency (f
500 kHz ≤ f
≤ 10 MHz
XP
500 kHz ≤ f
≤ 5 MHz
XP
2 MHz (TYP.) ≤ f
≤ 8 MHz (TYP.)
XP
2 MHz (TYP.) ≤ f
≤ 4 MHz (TYP.)
XP
4 .1 Option Byte
2 8 H
) are
XP
)
XP
) of the
POC
Setting.
17

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