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of the current character, the next full character may be sent, and then transmission
will be stopped.) When CTS is asserted once more, transmission will continue
where it left off. No CTS lost error will be reported. No characters except idles will
be transmitted while CTS is negated.
7 ASYNC-HDLC Rx Buffer Descriptor
The ASYNC-HDLC controller uses the Rx BD to report information about the received data
for each buffer. An example of the Rx BD process is shown in Figure 7-52 of the User's Man-
ual.
The first word of the Rx BD contains control and status bits. Bits 12 to 15 and bit 9 are written
by the user; bits 0-7 and 10-11 are set by the CP following frame reception. Bit 15 is set by
the core when the buffer is available to the ASYNC HDLC controller, and it is cleared by the
ASYNC HDLC controller when the buffer is full. The format of the control and status word is
detailed below.
15
14
OFFSET + 0
E
-
OFFSET + 2
OFFSET + 4
OFFSET + 6
Note: Entries in boldface must be initialized by the user.
E—Empty
0— The data buffer associated with this BD has been filled with received data, or data
reception has been aborted due to an error condition. The CPU32+ core is free to
examine or write to any fields of this Rx BD. The CP will not use this BD again while
the E-bit remains zero.
1— The data buffer associated with this BD is empty, or reception is currently in
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
Bits 14, 8, 6-4—Reserved, should be set to zero
W—Wrap (Final BD in Table)
0— This is not the last buffer descriptor in the Rx BD table.
1— This is the last buffer descriptor in the Rx BD table. After this buffer has been used,
the CP will receive incoming data into the first BD in the table (the BD pointed to
by RBASE). The number of Rx BDs in this table is programmable, and is deter-
mined only by the W-bit and the overall space constraints of the dual-port RAM.
I—Interrupt
0— The RXB bit in the ASYNC HDLC Event Register will not be set after this buffer has
been used, but RXF operation remains unaffected.
1— The RXB or RXF bit in the ASYNC HDLC Event Register will be set when this buff-
er has been used by the ASYNC HDLC controller.
MOTOROLA
Freescale Semiconductor, Inc.
13
12
11
10
9
W
I
L
F
CM
RX DATA BUFFER POINTER
For More Information On This Product,
Go to: www.freescale.com
8
7
6
5
-
BRK
-
-
DATA LENGTH
Asynchronous HDLC
4
3
2
1
0
I
AB
CR
OV
CD
16
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