4-3. FUNCTIONAL BLOCK DIAGRAM
OTW
Internal Pullup
Resistors to VREG
SD
M1
M2
M3
RESET_AB
RESET_CD
PWM
PWM_D
PWM
PWM_C
PWM
PWM_B
PWM
PWM_A
Protection
and
I/O Logic
Ctrl.
Timing
Rcv.
Ctrl.
Timing
Rcv.
Ctrl.
Timing
Rcv.
Ctrl.
Timing
Rcv.
Under-
4
voltage
Protection
VREG
Power
On
Reset
Temp.
Sense
Overload
Isense
Protection
Gate
Drive
Gate
Drive
Gate
Drive
Gate
Drive
3-36
VDD
VREG
AGND
GND
OC_ADJ
GVDD_D
BST_D
PVDD_D
OUT_D
BTL/PBTL Configuration
Pulldown Resistor
GND_D
GVDD_C
BST_C
PVDD_C
OUT_C
BTL/PBTL Configuration
Pulldown Resistor
GND_C
GVDD_B
BST_B
PVDD_B
OUT_B
BTL/PBTL Configuration
Pulldown Resistor
GND_B
GVDD_A
BST_A
PVDD_A
OUT_A
BTL/PBTL Configuration
Pulldown Resistor
GND_A