Dh-Board Block Diagram - Panasonic TH-42PZ70B Service Manual

TH-42PZ70B / TH-42PZ70E / TH-42PY70F / TH-42PY70P

15.32. DH-Board Block Diagram

DH FULL HD
TO
DH25
DG25
MAIN 3.3V 1
MAIN 3.3V 3 2
SUB5V
SUB 5V 75 74
SUB 9V 65 64
FHD9V
SUB 9V 63 62
LVDS_PD
LVDS_PD 6
OSD_FLAG
OSD_FLAG 7
TV_MAIN_ON
TV_MAIN_ON 10
FPGA_RST
FPGA_RST 11
CONFIG_DONE
CONFIG_DONE 12
GC_RESET
HQ1_XRST 47
CLKIA
CLKIA 107
VSIA
VSIA 105
HSIA
HSIA
104
BOE9 102
BOE2-BOE9
BOE2 (GYIA0-7)
95
GOE9
93
GOE2-GOE9
GOE2 86 (RVIA3,5-7)
(BUIA3,4,6,7)
ROE9 84
ROE2-ROE9
ROE2 (RVIA0-2,4)
77
(BUIA0-2,5)
LOSD15 14 PEAKS_OSD0-OSD15
LOSD0 30
PEAKS_OSDCK
PEAKS_OSDCK 32
PEAKS_OSDH
PEAKS_OSDH 34
PEAKS_YS
PEAKS_YS 35
PEAKS_YM
PEAKS_YM 36
PEAKS_OSVO
PEAKS_OSVO 37
PEAKS_OSHO
PEAKS_OSHO 38
PEAKS_OSCKO
PEAKS_OSCKO 40
SCL0 42 SCL0
SDA0 43 SDA0
TDO(TO SC) 49
TDI(TO HQ1) 50 JTAG
TCK 51
TRST,TMS 52 53
TRST 60
CFG_JTAG
TCK,TMS 59 58
TDO,TDI 57 56
FOR
FACTORY
DH4
USE
WP 2
SCL 4
SDA 5
TH-42PY70F/P, PZ70B/E
DH-Board Block Diagram
IC5001
IC5002
AVR 3.3V
SUB5V
DDR 2.5V
1 VOUT 5
VDD
CE
FHD3.3V
5 VOUT
3
IC5012
PLLAVDD_DDR AVDD_DDRCLK AVDD_DDR
AVR 3.3V
1 VDD VOUT 5 DAC_VDD
CE VDD_PLL2
3
FHQCKIN
VDD_PLL1
FHQVIN
FHD1.2V
FHQHIN
PORT-THQ
VDD12
FHQYIN0-9
CLKIA
FHQCIN0-9
CLKIA
VSIA
VSIA
PORT-A
CLK0THQ1
HSIA
HSIA
(ADV)
THQVOUT
THQHOUT
RVIA0-7
GYIA0-7
THQYO0-9
BUIA0-7
THQCO0-9
NRST X5000
XTALOUT
XTALIN
IC5100
GC5P_1st
CLK02
PORT-E
OSDI0-7 PTVEN
CLK0E
(OUTPUT
OSDI8-15
VS0E
FOR PANEL)
HS0E
PORT-D
CLKID
(H264)
VSI BOE0-9
HSI GOE0-9
ROE0-9
TRST
VDD25
TCK
JTAG
TMS
DATA BUS
TDI DQ0-DQ31
TDO
ADDRESS BUS
A0-A11
SCL0 SCL
SDA0 SDA
BA0,BA1
DQS0-DQS3 CONTROL BUS
SCL_MC
CKE,WE
RAS,CAS
SDA_MC
SDCLK0,NSDCL0
30 OVP
18 OUT2-1
FHD9V
20 OUT2-2
G2 S2 G1 S1
19 LX2
D2 D2 D1 D1
8 -INC2
Q5902
FHD1.2V
IC5000
12 VO2
64k EEPROM 11
FB2
FHD3.3V
7 WC VCC 8
6 SCL
5 SDA
FHD3.3V
VDD 1
FRCK_FPGA
IC5013
RESET
FHD3.3V
2 VDD OUT 4
SCL0 Q5001
SDA0 Q5000
FPGA_RST
1DDR2.5V
LVDS_PD
CONFIG_DONE
DQ0-DQ31
IC5006
PEAKS_OSDCK
AVR 2.5V FHD3.3V
A0-A11
PEAKS_OSDH
BA0,BA1
VDD 1 8 PEAKS_YS
VOUT VDD
DQS0-DQS3
VDDQ
PEAKS_YM
CKE,WE
RAS,CAS
PEAKS_OSVO
CK,CK
PEAKS_OSHO
PEAKS_OSCKO
IC5102
OSD_FLAG
DDR-SDRAM
IC5901
DC-DC CONVERTER
FHD9V
9V->1.2V,9V->3.3V
16 27 17 21
CTL CB1 CB2 VB
23 IC5003
VCC
OSD-FIFO
FHD3.3V
OUT1-1 26
VCC
DATA BUS
OUT1-2 24
DI0-DI31
G2 S2 G1 S1
DATA BUS
25
LX1
DO0-DO31
D2 D2 D1 D1
SRCK,SWCK CONTROL BUS
-INC1 7
RSTR,RSTW
Q5901
RE,WE
VO1 3
FHD3.3V
4
FB1
96
IC5009 IC5008
AVR 2.5V AVR 1.5V
FHD3.3V
8 VIN VOUT 1 8 VIN VOUT 1
VCCI01 VCCI02 VCCI04
FRCLKIN
27MHz
VCCI03
NCFG
VCCINT
VCCA_PLL1
PTVEN
VCCA_PLL2
CLK0E
VS0E
HS0E
BOE0-9
IC5105
GOE0-9
FPGA
ROE0-9
(CYCLONE) RE_E+
SCL RE_E-
RD_E+
SDA RD_E-
RC_E+
RC_E-
NRST
RB_E+
RB_E-
LVDS_PD RA_E+
RA_E-
CONF_DONE
RCLK E+
PEAKS_OSDCK
RCLK E-
PEAKS_OSDH
PEAKS_YS
RCLK O+
PEAKS_YM
RCLK O-
PEAKS_OSVO RE O+
RE O-
PEAKS_OSHO
RD O+
PEAKS_OSCKO
RD O-
OSD_FLAG
RC O+
RC O-
RB O+
PEAKS
RB O-
OSD0-15
RA O+
RA O-
IC5010
FHD3.3V CONFIG ROM
3 VCC
DCLK 6 DCLK
ASDO 5 ASDI
OSD_DI0-DI31
DATAO 2 DATA
OSD_DO0-31
nCSO 1 NCS
OSD_SRCK,SWCK
OSD_RSTR,RSTW
OSD_RE,WE TCK
CFG-JTAG
TMS
TDI
TDO
TH-42PY70F/P, PZ70B/E
DH-Board Block Diagram
DH5 TO D5
1 E+LVDS0
2 E-LVDS0
4 E+LVDS1
5 E-LVDS1
6 E+LVDS2
7 E-LVDS2
9 E+LVDS3
10 E-LVDS3
11 E+LVDS4
12 E-LVDS4
14 E+LVDSCLK
15 E-LVDSCLK
16 LVDS_DET
17 0+LVDSCLK
18 0-LVDSCLK
20 0+LVDS0
21 0-LVDS0
23 0+LVDS1
24 0-LVDS1
25 0+LVDS2
26 0-LVDS2
28 0+LVDS3
29 0-LVDS3
30 0+LVDS4
31 0-LVDS4