Byte Enable Behavior; Address Clock Enable Support - Intel Agilex User Manual

2.1.3. Byte Enable Behavior

Figure 1. Byte Enable Functional Waveform
This figure shows how the
current data: q (asynch)

2.2. Address Clock Enable Support

Intel Agilex embedded memory blocks support address clock enable. When you enable
address clock enable (
Note: 1. Only simple dual-port mode supports this feature.
2. The
addressstall
can result the output having non-deterministic values.
When you configure the memory blocks in dual-port mode, each port has its own
independent address clock enable.
® ™
Intel Agilex Embedded Memory User Guide
8
and
wren byteena
inclock
wren
address an a0
data XXXXXXXX
byteena XXXX 1000
contents at a0 FFFFFFFF
contents at a1 FFFFFFFF
contents at a2 FFFFFFFF
contents at a3
contents at a4
doutn
addressstall
signal cannot be asserted during the first clock cycle as this
2. Intel Agilex Embedded Memory Architecture and Features
signals control the operations of the embedded memory blocks.
a1 a2
ABCDEF12
0100 0010 0001
ABFFFFFF
FFFFFFFF
FFFFFFFF
ABFFFFFF FFCDFFFF FFFFEFFF
= 1), it holds the previous address value.
UG-20208 | 2019.04.02
a3 a4 a0
XXXXXXXX
1111 XXXX
FFCDFFFF
FFFFEFFF
FFFFFF12
ABCDEF12
FFFFFF12 ABCDEF12 ABFFFFFF
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