Blt; Bltu - Intel NIOS II Owner Reference Manual

8. Instruction Set Reference
NII-PRG | 2018.04.18
Example
Description
Pseudo-instruction

8.5.13. blt

Instruction
Operation
Assembler Syntax
Example
Description
Exceptions
Instruction Type
Instruction Fields
31 30 29
A
15 14 13

8.5.14. bltu

Instruction
Operation
Assembler Syntax
Example
Description
28 27 26 25
12 11 10 9
IMM16
bleu r6, r7, top_of_loop
If (unsigned) rA <= (unsigned) rB, then
program counter to the instruction at label.
is implemented with the
bleu
the register operands.
branch if less than signed
if ((signed) rA < (signed) rB)
then PC PC + 4 + σ(IMM16)
else PC PC + 4
blt rA, rB, label
blt r6, r7, top_of_loop
If (signed) rA < (signed) rB, then
control to the instruction at label. In the instruction
encoding, the offset given by IMM16 is treated as a signed
number of bytes relative to the instruction immediately
following . The two least-significant bits of IMM16 are
blt
always zero, because instruction addresses must be word-
aligned.
Misaligned destination address
I
= Register index of operand rA
A
= Register index of operand rB
B
= 16-bit signed immediate value
IMM16
Bit Fields
24 23 22 21
B
8 7 6 5
branch if less than unsigned
if ((unsigned) rA < (unsigned) rB)
then PC PC + 4 + σ(IMM16)
else PC PC + 4
bltu rA, rB, label
bltu r6, r7, top_of_loop
If (unsigned) rA < (unsigned) rB, then
program control to the instruction at label. In the instruction
encoding, the offset given by IMM16 is treated as a signed
number of bytes relative to the instruction immediately
following . The two least-significant bits of IMM16 are
bltu
always zero, because instruction addresses must be word-
aligned.
transfers
bleu
instruction by swapping
bgeu
transfers program
blt
20 19 18 17
IMM16
4 3 2 1
0x16
transfers
bltu
continued...
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