Sony MZ-E30 Service Manual
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Sony MZ-E30 Service Manual

Sony MZ-E30 Service Manual

Portable mini disc player
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  • Page 17 NEW TECHNICAL THEORY FOR SERVICING MZ-E30 OPERATION MANUAL PORTABLE MINI DISC PLAYER — 1 —...

  • Page 18: Table Of Contents

    TABLE OF CONTENTS Section Title Page 1. DIAGRAMS 1-1. BLOCK DIAGRAM ............................3 2. FUNCTIONS AND FEATURES 2-1. Principal Features ............................. 6 3. Difference in System Configurations by Generation 3-1. System Block Diagrams ........................... 8 4. OUTLINE OF SYSTEM 4-1. Microprocessor Interface ..........................
  • Page 21 In the case of a playback type model heretofore available, a playback circuit and a decoder circuit have been employed while jointly using the principal LSI with a recorder/playback unit. The MZ-E30, however, employs an newly developed LSI for the exclusive use of playback, which has especially main functions, such as shock-proof, ATRAC decoding, EFM decoding and ACIRC decoding.

  • Page 22: System Block Diagrams

    3-1. System Block Diagrams The playback type Mini Discs belonging to the first thru 4th generations have their respective systems composed of the blocks illustrated below. (1) 1st Generation [MZ-2P] 4M DRAM ADIP ATRAC(L) CXD2527 CXA1380 SHOCK PROOF AUDIO D/A CONV. ACIRC OUTPUT AK4501...
  • Page 23 CXD2536 OPTICAL BLOCK RF AMP. CXD2535 KMS-201 CXA1981 DRIVE SYSTEM CONTROLLER MPC17A38 Fig. 3-3. 3rd Generation Mini Disc System Block Diagram (4) 4th Generation [MZ-E30] 4M DRAM EFM,ACIRC AUDIO SHOCK PLOOF D/A CONV. OUTPUT AK4314 ATRAC OPTICAL BLOCK DIGITAL SERVO RF AMP.

  • Page 24: Outline Of System

    Fig. 4-1. General System Block Diagram Fig. 4-1. is the general system block diagram. The MZ-E30 belonging to the fourth generation is generally composed of the system controller (IC801) to control the system as a whole as illustrated in the figure. In addition, a digital signal processor and a digital servo system are mainly composed of the DSP/digital servo LSI µPD63730GC (IC601) for playback.

  • Page 25: Microprocessor Interface

    Fig. 4-2. Outline of Microprocessor Interface The MZ-E30 has a microprocessor interface outlined in Fig. 4-2.. As shown in the figure, the system controller (IC801) is employed as the mainstay to control the system as a whole. Besides, the DSP/digital servo (IC601) and the EEP ROM (IC802) are provided.
  • Page 26 In the conventional model, moreover, the sound volume setting data and the address data relating to the stop position applied in the resume function are held in the RAM located in the interior of the system controller normally powered. In the MZ-E30, however, the power will stop being supplied to the system controller if the stop mode should last for about 10 second (which varies with an optical block position and/or with a mode) for the purpose of saving the energy.
  • Page 27 (2) Reading onto System Controller from DSP/Digital Servo To read from the DSP/digital servo, the information transferred to the system controller is limited to data only but free from Bit 3 “D/C” as shown in Fig. 4-5.. The DSP/digital servo has an SBUS terminal employed as an output port only during the bit period for which data are being output.

  • Page 28: Clock System

    4-2. Clock System IC803 SLED MOTOR (48fs) CONTROL IC601 DSP/DIGITAL SERVO EFM/ACIRC DECODER CONTROLLER IC301 IC801 D/A CONVERTER SYSTEM CONTROLLER (48fs) TIMING (96fs) GENERATOR LRCK LRCK (fs) from RF AMP IC501 pin RF-OUT X301 (384fs) (4fs) (384fs) (384fs) IC901 DC-DC CONVERTER NOTE : fs = 44.1[kHz] Fig.

  • Page 29: Power Supply Circuit

    5. POWER SUPPLY CIRCUIT Fig. 5-1. shows an outline of the power supply circuit employed in the MZ-E30, as shown in the figure, the power supply voltages applied to the MZ-E30 may be divided, if roughly classified, into three: 1.5V, 2.8V and 2.5V lines. 2.8V (VC) is obtained by raising the 1.5V voltage in the step up circuit (2) and supplied to principal circuits, such as D/A converter (IC301),...

  • Page 30: Outline Of Power Supply Circuit Operation

    5-1. Outline of Power supply Circuit Operation Fig. 5-2. shows the power supply circuit block diagram and timing of waveforms in wakeup (startup) and sleep (standby) modes. Operating a key on the unit or in the remote commander connected to Pin #∞ [XWK1] thru Pin #™ [XWK4] in the DC-DC converter (IC901) will cause the related input pin to become “L,”...

  • Page 34: Detecting Decrease In Voltage

    R801 and R802. And the voltage so halved is input to Pin 2 [UREG MON] in the system controller, thereby detecting a decrease in voltage. A battery voltage of 0.8V or less will cause the MZ-E30 to be put into the STOP mode, with Message “LoBATT”...

  • Page 35: Reset Circuit

    5-5. RESET Circuit Fig. 5-7. shows the RESET circuit and the RESET signal timing. The 2.8V (VC) obtained in the step up power supply circuit of the motor driver (IC551) enters the RESET circuit after being divided with a resistor inside via Pin 0 [VC] in the DC-DC converter (IC901).

  • Page 36: System Control

    (a) Example of MZ-E3 IC801 SYSTEM CONTROLLER HOLD SW HOLD S802 PLAY AVLS SW AVLS PLAY S805 OPN/CLS SW SWITCH OPEN/CLOSE S801 MATRIX REMOTE CONTROLLER UNIT (SWITCH MATRIX) (b) MZ-E30 Fig. 6-1. Detection Switch Connected to System Controller — 27 —...
  • Page 37 6-2. Key Input Detection of Operation Buttons The operation buttons on the unit and remote commander are each composed of switch matrix by combining with the dividing resistor. As shown in Fig. 6-1. (b), when a operation button on the unit or a operation button on the remote control unit is pressed, the voltage corresponding to the mode determined by the dividing resistor is input to Pin 8 [SET KEY] or Pin 7 [REM KEY] of the system controller (IC801) respectively.
  • Page 38 (2) When operating using the remote commander Fig. 6-3. shows the connection between the operation buttons on the remote commander and the system controller (IC801) while Table 6-2. shows the dividing voltage input to Pin 7 [RMC KEY] of the system controller when a remote commander button is pressed.
  • Page 39 6-3. operation of APC Circuit and Laser Power 2.8[V](VC) IC501 RF AMP LD-VDD IC801 R506 SYSTEM CONTROLLER PD-O LD-SNS (2.7[V]) R504 C506 Q501 LD-DRV R883 PD-I APCREF LD DRIVE (2fs) CN501 C806 PD-IN ILCC LDGND SSB-I/F KGND APPROX.4.6[s] APPROX.1.8[s] 2.7[V] IC801 SYSTEM CONTROLER 41 pin APCREF 2[V]...
  • Page 40 In models which can record, changes in the recording power of the disc according to the ambient temperature and internal temperature of the unit are detected by the temperature sensor and compensated. The RF amplifier (IC501) has a function which converts temperature into voltage and outputs it from Pin !• (VTEMP), but this function is not used in this unit intended exclusively for playback.

  • Page 41: Playback Circuit

    7. PLAYBACK CIRCUIT 7-1. Outline of Playback Circuit Fig. 7-1. shows the structure of the playback circuit of the Mini Disc. The RF data read by the optical block is demodulated by the EFM demodulator, and data errors are detected and corrected by the ACIRC decoder. Since the Mini Disc data has the same structure as the CD-ROM, it is decoded in the CD-ROM decoder in the next step, and the ATRAC data compressed to approximately 1/5 is stored in the shock proof memory (buffer RAM).

  • Page 42: Digital Dbb And Mute Circuit

    The D/A converter is also incorporated with a digital DBB (Dynamic Bass Boost) and eight times over sampling digital filter. These perform boosting of low bands and data filtering respectively using digital signals. The D/A converter also has a deemphasis function, which is controlled using the emphasis ON and OFF signals output from Pin #• (EMP) of the DSP/ digital servo.

  • Page 43: Servo Circuit

    8. SERVO CIRCUIT 8-1. Outline of Servo Circuit IC551(1/2) SERVO DRIVER FE/TE FOCUS RF/ADIP IC601 FOCUS IC501 COIL DSP/ RF AMP DIGITAL SERVO OPTICAL TRACKING TRACKING PICK-UP COIL ODX-01 IC551(2/2) SERVO DRIVER SPINDLE IC801 SPINDLE MOTOR IC803 SYSTEM SLED CONTROLLER SLED SLED MOTOR...

  • Page 44: Intermittent Operations Of Servo

    8-2. Intermittent Operations of Servo The focus servo and tracking servo of this unit turn ON and OFF repeatedly during normal playback and operate intermittently. To save power, they repeat 1.8 seconds of ON and 2.8 seconds of OFF as shown in the timing chart in Fig. 8-2. along with the switching of the laser diode to ON/OFF.
  • Page 45 In 4th generation playback only players, improvements of the optical block enabled detection of the MO media to be performed properly even when search was carried out from the far side of the disc as the disc surface deviated from the focusing range.

  • Page 46: Focus Servo Circuit

    8-4. Focus Servo Circuit As shown in Fig. 8-5., the photoelectric current output from the optical block A to D detectors is input to the RF amplifier (IC501), converted to voltage by the I-V amplifier inside, passed through the ABCD amplifier and F.E. (focus error) amplifier, and the ABCD signal is output from Pin #∞...
  • Page 51 Internal Block Diagram FR-OUT DFCT DFCT MIRROR OFTRK OFTRK OFTIN ABCD ABCD conversion MIRR-VTH conversion Focus-Error conversion ADIP ADIP BPF ADIP conversion BPFC0 BPFC1 REXT2 conversion FE and TE conversion T-COUNT T-COUNT EXT-IN REXT1 PD-IN Thermometer VTEMP PD-I A-VDD PD-O LD-SNS A-VDD D-VDD...
  • Page 52 Pin Assignment 36 FE ABCD OFTIN AGND REXT2 BPFC0 SN761050A BPFC1 A-VDD ADIP T-COUNT EXT-IN PD-IN DFCT PD-I OFTRK — 56 —...
  • Page 53 Pin Function Pin No. Symbol Function E current input D current input C current input F current input AGND — Analog GND I voltage input J voltage input A-VDD — Analog Vdd B current input A current input PD-IN PD AMP non-inverted input PD-I PD AMP inverted input PD-O...

  • Page 54: Dsp/Digital Servo Μpd63730Gc

    10-2. DSP/Digital Servo µPD63730GC DSP/digital servo for MD playback • Built-in ATRAC decoder for playback • Digital servo, EFM decoder, and ACIRC decoder functions uPD63730GC — 58 —...
  • Page 55 Internal Block Diagram DREQ MCK/2 XATWE DRD 0-3 ATDT RESET SINT DRA 0-11 AC-WDCK SBUS TEST S-DATA XWE2 M0CK M00-3 XOE2 M1CK M10-3 XCAS ERFLAG RD-DT-ECC XRAS WRREQ etc. SOREQ CRCF ECC-DATA 2nd MSB EFM-DATA-A/B PLCK ADIP-DATA TFOUT ADPLCK TROUT FROUT FFOUT —...
  • Page 56 Pin Configuration 50 MCK MCK-I/O MICK MCK/2 MOCK PMCK DOUT AUDATA LRCK uPD63730GC PLCK ADPLCK ADIP-DATA TEST XBUSY SINT CRCF ERFLAG SBUS RESET — 60 —...
  • Page 57 Pin Function Pin No. Symbol Function VDD ADC — Power supply for ADC block VREF Reference voltage input RF signal input Focus error input ABCD ABCD (all quantity of light) signal input Tracking error input ADIP ADIP signal input ADC high potential reference voltage for RF ADC low potential reference voltage for other than RF VSS ADC —...
  • Page 58 Pin No. Symbol Function — Power supply DRD0 DRAM data input/output DRD1 DRAM data input/output DRAM write enable output XWE2 DRAM write enable output — Ground DRD3 DRAM data input/output DRD2 DRAM data input/output XCAS DRAM-CAS output DRAM output enable output XOE2 DRAM output enable output DRA9...

  • Page 59: Servo Driver Mpc17A55Fta

    10-3. Servo Driver MPC17A55FTA MD/CD player motor driver, system power supply MPC17A55FTA — 63 —...
  • Page 60 Internal Block Diagram 3 Phese Pre driver Control Pre driver Control Pre driver Control int OE D0 or D1 BIAS int STB Control Slep-Up/Down /Power SW Decoder Power SW Pre driver H-Bridge Pre driver Control Slep-Up/Down Pre driver DCC2 H-Bridge Pre driver Control Slep-Up...
  • Page 61 Pin Function Pin No. Symbol Function Operation mode setting Power switch input 1 Power switch input 1 Power switch output Power switch output Power switch input 2 Step up/down converter PWM output GND DCC2 — Step up/down converter GND Step up/down converter fixed pulse output DC/DC converter output DC/DC converter output Step up converter PWM output...
  • Page 62 Pin No. Symbol Function GND H13 Power GND for the H bridge driver H bridge driver 1 output H bridge driver 1 power supply H bridge driver 1 output GND H12 Power GND for the H bridge driver H bridge driver 2 output H bridge driver 2 power supply H bridge driver 2 output GND H2...
  • Page 63 Outline of Operations (1) Power Switch, DC/DC Block Slep-Up/Down /Power SW Decoder Power SW Pre driver Slep-Up/Down 10uH 47uH VCON DCC2 Pre driver 33uF Slep-Up Pre driver DCC1 DCC1 Fig. 1 Power Switch, DC/DC Section As shown in Truth Table 1, in the power switch, the VB1 and VB2 voltages are output to the VB terminal by the combination of D0 and D1.
  • Page 64 (2) Bias control block int OE D0 or D1 BIAS int STB Slep-Up/Down Control /Power SW Decoder Fig. 2 Bias operation Block The two signals Int STB, Int OE shown in the truth table are made from the D0, D1, OE, and VC voltages. These two signals are not output to outside, and are used to switch the power switch, circuit blocks other than the DC/DC block to the standby or operating state.
  • Page 65 (4) 3-Phase Driver 3 Phese Pre driver Control PGND PGND Fig. 4 3-Phase Driver The 3-phase motor driver is composed of three half-bridges. This driver also sets into the standby state when Int OE is “L”, and its output is fixed at “L” regardless of the input logic. When Int OE becomes “H”, the driver sets into the operating state. The ON resistors M5 to M10 are each 0.5 Ω...
  • Page 66 (6) 3-Phase Comparator Fig. 6 3-Phase Comparator This comparator is used for detecting the phase of the 3-phase motor driver. The IN terminal of one pin is commonly used for + input terminal. – input terminal is commonly used for each of the three 3-phase driver outputs. When the Int STB signal is “L”, the output is fixed at “L”, and operates at “H”.

  • Page 67: Dc-Dc Converter Mpc1830Vmel

    10-4. DC-DC Converter MPC1830VMEL Power Supply for System for MD/CD Player MPC1830VMEL — 71 —...
  • Page 68 Internal Block VSTB VRMC XWK1 BANDGAP REFERENCE XWK2 VRFE SYSTEM XWK3 CONTROL XWK4 FFCLR CRST SLEEP RESET XRST VBSEL VB SELECT VBMON SPCKO SPCK BUFF SPCK1 OSC1 STEP-UP PGND DC/DC CONVERTER PWM1 CHARGE PWM1 PUMP MODE SELECT OSC2 VG 18 VCON —...
  • Page 69 Pin Functions Pin No. Symbol Function GND pin of control block VRMC SW output for remote commander VREF Connected to capacitor for reference voltage output pin filter. Switching power supply control circuit error amplifier inverted input pin Switching power supply control circuit error amplifier feedback resistor connection output pin Switching power supply control circuit dead time control pin CRST Reset circuit reset signal delay capacitor connection pin...
  • Page 70 Outline of Operations Latch5 Latch1 Wake XWK1 The start circuit operates when the wake terminal becomes HIGH. Latch2 XWK2 Latches at the rising edge of Latch 1 to 4. Latches when Latch 5 becomes H from L. Latch3 Latching is set at the falling edge of XWK1 to XWK4, and XWK3 wake is output.
  • Page 71 When XRST is H, D0 becomes L and D1 becomes H, and M2 XRST turns ON, and M1 goes OFF. When D0 becomes H, M2 goes OFF, and M1 turns ON. When D0:L D1:H (using VB1) VG=3×VC When D0:H D1:H or L (using VB2) VG=VB+2×VC Charge Pump Circuit VBH is output with the higher voltage between VB2 and VB1.
  • Page 72 XRST When VC reaches 88% of the expected value, the output of the comparator becomes L, M1 and M2 go OFF, and as a result CRST XRST becomes H. The timing can also be delayed using the capacitor attached externally to CRST. XRST (INT) Reset Circuit...

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