NAD T737 Service Manual page 23

Pin No. Mnemonic
72, 74, 76,
53, 55, 57,
71, 73, 75
42, 41, 28, P2–P9, P12–
27, 26, 25, P19
23, 22, 10,
9, 8, 7, 94,
93, 92, 91
44, 43, 21, P0–P1, P10–
20, 45, 34, P11, P20–P21,
33, 32, 31, P22-P25 P26-
30, 29, 24, P29
14, 13
2, 1, 100, P31–P40
97, 96, 95,
88, 87, 84,
83
3 INT
4 HS/CS
99 VS
98 FIELD/DE
81, 19 SDA1, SDA2
82, 16 SCLK1,
SCLK2
80 ALSB
78 RESET
36 LLC1
38 XTAL
37 XTAL1
Type Function
O Video pixel output port.
I/O Video pixel input/output port.
I Video pixel input port.
O Interrupt pin, can be active low or active high. When SDP/CP
status bits change this pin will trigger. The set of events which
will trigger an interrupt are under user control.
O HS is a horizontal synchronization output signal in SDP and
CP modes. CS is a digital composite synchronization signal
that can be selected while in CP mode.
O VS is a vertical synchronization output signal in SDP and CP
modes.
O FIELD is a field synchronization output signal in all
interlaced video modes. This pin also can be enabled as a DE
(Data Enable) signal in CP mode to allow direct connection to
a HDMI/DVI Tx IC.
2
I/O I C port serial data input/output pin, SDA1 is the data line for
the Control port and SDA2 is the data line for the VBI
readback port.
2
I I C port serial clock input (max clock rate of 400 kHz).
SCLK1 is the clock line for the Control port and SCLK2 is
the clock line for the VBI data readback port.
I This pin selects the I
VBI readback ports. ALSB set to a logic 0 sets the address for
a write to control port of 0x40 and the readback address for
the VBI port of 0x21. ALSB set to a logic high sets the
address for a write to control port of 0x42 and the readback
address for the VBI port of 0x23.
I System reset input, active low. A minimum low reset pulse
width of 5 ms is required to reset the ADV7403 circuitry.
O LLC1 is a line locked output clock for the pixel data (range is
13.5MHz to 110MHz).
I Input pin for 28.6363 MHz crystal, or can be overdriven by an
external 3.3 V 28.6363 MHz clock oscillator source to clock
the ADV7403.
O This pin should be connected to the 28.6363 MHz crystal or
left as a no connect if an external 3.3 V 28.6363 MHz clock
oscillator source is used to clock the ADV7403. In crystal
2-10
2
C address for the ADV7403 Control and
ADV7403