Overview; Functional Blocks Description; Amplifier Stages; Biasing And Mute_1Not - Crown XTi series Service Manual

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Cequal Amplifier Operation Details
1.0

OVERVIEW

Note: Sketches and waveform tifs have been added to this section to clarify the various concepts
related to the amplifier and its system level behavior.
For XTI 1000 and DSI 1000 amplifier schematics with voltage and currents references, use
channel 1 of 139087-6ref.tif which is sheet 4.
Amplifier heat sinks are tied to +/- Vbulk.
For XTI2000, DSI2000, CDI1000, CDI2000 amplifier schematics with voltage and currents
references, use channel 1 of 139086-6ref.tif which is sheet 4.
Amplifier heat sinks are tied to moving tracker voltages.Below is using 138086-6ref.tif channel 1
of XTI2000 (Also, see REPAIRnotes.txt) and (Notes below) for root cause and repair.

Functional Blocks Description

1) Amplifier stages

a) Biasing and Mute_1not
Bias is developed with the general components D117, D118, Q100, R104, D134, R182, C102,
R107, and Q102. Bias is on when D117 and D118 are allow to conduct, so the base of Q100 will
sit at about +2.4Vdc (4 diode drops.). This is a 3 state node, it gets control from the DSP via
Mute1_not, normally +3V (ON) , 0V (OFF) , the LM75 sensor under HS1 (+Vbulk) sink at +3V
(ON) when not over temp, about 100 deg C, and the DCLF / Low Vbulk comparator U103A,B
also in a high output (pulled up thru R325 to +15V) state. All four controls must be good in
order for bias to come up. If all four controls are good, than Q100 base will be about +2.4Vdc.
If the Mute1_not is good from the DSP, and the comparator Q103 goes low due to either low
Vbulk ( < 60% of nominal rail +/- voltage) or too much DC for too long a time on the amplifier
output terminals then Q100 base (10Hz@vmax) will go to about +1.0Vdc from the +2.4V. At
that moment when Q100 base went down to the 2
is now discharging. If the DC on the output of the amplifier is there long enough and/or high
enough level then C102 will discharge enough to cut the bias to off and mute the amplifier and
let its output return back to zero volts. Thus C102 lets some DC for a level and time before a
protect via mute is activiated. If the DSP or the LM75 sensor tells the amplifier to mute ,3
state, but not the local comparator DCLF path then when they go low the base of Q100 will be
about 0-0.6Vdc negative, being clamped there by D126 . Time estimates for C102 from a mute
command to actual mute is about 30ms. If a large LF output is there but not long enough you
might see a DCLF at U103 but C102 will still hold up the bias. Mute1_not could be a write or a
read state line.
b) Input differential stage
The differential input stage consists of Q103, Q104, and Q116 and Q134, getting its bias from
Q102. Q102s current source is divided evenly to Q103 and Q104. The bases of Q116 and Q134
are set to about -13.5v with R78 and R79. This locks the collectors of both Q103 and Q104 to
about -13V no matter what. This removes high and unequal voltages from them. So Q116 and
Q134 just pass current and take the heat. See note 1 below for Q116 and Q134.
c) Error gain amplifier and bias servo
The error gain amplifier and bias servo are set up with Q105, Q107, with the measurable
amplified error signal of the total amplifier at the opposite end of R133 from Q105 (see note 3).
Qperating currents of this stage is scaled for higher voltage product over the XTI1000. It is gated
and controlled the bases of Q107 and Q108 (A and B on the schematic, with approximate
voltages with respect to C the –Vbulk.). Q141 (in high voltage units) is for distributing the
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nd
state, Q100 is off but C102, the hold-up cap
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Rev A 8-28-2006 AA
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