Schematic Diagram - Samsung GT-E1120 Service Manual

12. Schematic Diagram

- NC Point
-Main Chip
6. Pinning in format io n
12345678
A
RFOH RFOL GND_RF VDD_RF
NO_CON
B
GND_RF GND_RF VDD_RF
NECT
NO_CON
C
GND_RF
NECT
D
RFID_P GND_RF GND_RF
E
RFID_N GND_RF GND_RF
F
RFIE_P GND_RF VDD_RF
G
RFIE_N GND_RF GPIO8
H
GND_RF GND_RF GPIO38
J
GPIO39 GPIO52 GPIO57 VDD_VIO2
K
KEYIN0 KEYIN1 KEYIN2
L
KEYIO0 KEYIO1 KEYIO2
M
KEYOUT0 KEYOUT1 NTRST
N
KEYOUT2 KEYOUT3 TDI
P
TDO TCK RTCK
R
SSI_SEL0 TMS TEST
T
SSI_CLK SSI_SEL2 NRESET
U
SSI_DATA SSI_OUT
V
GPIO41 GPIO2 GPIO6 GPIO7
W
GPIO40 GPIO5 GPIO20 GPIO1
Fig 2. PNX4900 ball config urati on dia gram
9 10 11
XTAL_SH XTAL_26 XTAL_26 XTAL_SH GND_VC
ADDR16 NCS2
LD M_2 M_1 LD ORE
XTAL_SH XTAL_SH XTAL_SH XTAL_SH GND_VC
ADDR8 NWE0
LD LD LD LD ORE
GND_VC
GND_RF GND_RF GND_RF ADDR10 ADDR7 NBE0
ORE
GND_VC
GND_RF GND_RF GND_RF ADDR9 ADDR6 ADDR5
ORE
GND_RF
VDD_RF_I GND_VC GND_VC GND_VC GND_VC
ADDR11
O ORE ORE ORE ORE
GND_VC GND_VC GND_VC GND_VC GND_VC
GPIO10
ORE ORE ORE ORE ORE
GND_VC GND_VC GND_VC GND_VC GND_VC
ORE ORE ORE ORE ORE
VDD_VCO VDD_VCO VDD_VCO VDD_VCO VDD_VCO
VDD_VIO
RE RE RE RE RE
GND_VC VDD_VCO VDD_VCO VDD_VCO VDD_VCO VDD_VCO
ORE RE RE RE RE RE
GND_VC VDD_VCO VDD_VCO VDD_VCO VDD_VCO VDD_VCO
ORE RE RE RE RE RE
GND_VC GND_VC GND_VC GND_VC GND_VC
VDD_VIO
ORE ORE ORE ORE ORE
VDD_VIO
GND_GD NO_CON VBAT_SE GATE_RE GND_VC
VDD_VIO AUX_POK
GPA NECT NSE G ORE
PWM_OU PWM_OU PWM_OU VDD_GPP GND_VBA VBAT_DC
POK_IN
T1 T2 T0 M T_SNS DC
UART1_T THERM_I UART1_C ACC_DET
POK_OUT VCHG SWCORE
D N TS _IN
UART1_R UART1_R
LDO_EN ICHGN ICHGP GATE_SW SWCORE
D TS
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12 13 14 15 16 17 18
VDD_VME VDD_VME VDD_VME
NCS0 ADDR14 DATA6 DATA7
M1 M M
VDD_VME
NCS1 ADDR15 ADDR22 ADDR21 DATA12 DATA13
M
DATA15
NRESET_ VDD_VME
ADDR12 ADDR13 ADDR17 DATA11
OUT M
NBE1 NOE ADDR2 ADDR19 ADDR3 DATA10
ADDR18 ADDR4 DATA9
GND_VSI
ADDR1 ADDR20 SIM_RST DATA0
M
GND_VC VDD_VSI GND_GD NO_CON SIM_DAT
ORE M GPA NECT A
GND_VC GND_VC FE_CTRL FE_CTRL NO_CON
ORE ORE 0 1 NECT
VDD_VCO VDD_VCO FE_CTRL VDD_RFD UART0_T
RE RE 2 IG D
VDD_VCO VDD_VCO FE_CTRL CLK_32K_ UART0_R
RE RE 3 OUT D
VDD_VCO VDD_VCO GND_GD VBAT_RT
PA_RAMP
RE RE GPA C
GND_VC GND_VC VDD_GPP NO_CON NO_CON
ORE ORE M NECT NECT
AUXAUD_
GND_VBG VBG
IN_L
VBAT_AN VBAT_AN VDD_AUD VDD_AUD VDD_AUD AUXAUD_
A A IO_DRV IO_DRV IO IN_R
VBAT_DC GND_AUD GND_AUD GND_AUD INTMIC_BI
GND_SUB
DC _DRV _DRV _DRV AS
EXTMIC_
BIAS
VDD_VPE PMU_VSI PMU_VME
VCORE VCM_OUT VCM_OUT GND_AUD
RM M M
PMU_VPE PMU_VAN EAR_OUT EAR_OUT HSET_OU
PMU_VRF PMU_VIO
RM A _N/R _P/L T_N
12-1
19
DATA14
DATA5
DATA4
DATA3
DATA2
DATA1
DATA8
SIM_CLK
NO_CON
NECT
XTAL_32K
_2
XTAL_32K
_1
AUX_ADC
0
HKSW_D
ET2
HKSW_D
ET1
EXTMIC_I
N_N
EXTMIC_I
N_P
INTMIC_IN
_N
INTMIC_IN
_P
HSET_OU
T_P