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XL-SV320SL/305GD/308BU
ES3210 Pin description
Name
Number
VDD
1, 31, 51
RAS#
2
DWE#
3
DA[8:0]
12:4
DBUS[15:0]
28:13
RESET#
29
VSS
30,50,80,100
YUV[7:0]
39:32
VSYNC
40
HSYNC
41
CPUCLK
42
PCLK2X
43
PCLK
44
AUX[7.0]
54,52,53,49:45
LD[7:0]
62:55
LWR#
63
LOE#
64
LCS[3,1,0]#
65,66,67
LA[17:0]
87:82, 79:68
VPP
81
ACLK
88
AOUT
89
/SEL-PLLO
ATCLK
90
ATFS/
91
SEL-PLL
DOE#
92
AIN
93
ARCLK
94
ARFS
95
TDMCLK
96
TDMDR
97
TDMFS
98
CAS#
99
1-8
I/O
I
Voltage supply for 3.3V.
O
DRAM row address strobe (active low).
O
DRAM write enable (active low).
O
DRAM multiplexed row and column address bus.
I/O
DRAM data bus.
I
System rest (active low).
I
Ground.
O
Y is luminance, UV are chrominance data bus for screen video interface.
YUV[7:0] for 8-bit YUV mode.
I/O
Vertical sync for screen video interface. programmable for rising or falling edge.
I/O
Horizontal sync for screen video interface, programmable for rising or falling edge.
I
RISC and system clock input. CPUCLK is used only if SEL-PLL[1:0]=00.
I/O
Pixel clock; two times the actual pixel clock for screen video interface.
I/O
Pixel clock qualifier in for screen video interface.
I/O
Auxiliary control pins (AUX0 and AUX1 are open collectors).
I/O
RISC interface data bus.
O
RISC interface write enable (active low).
O
RISC interface output enable (active low).
O
RISC interface chip select (active low).
O
RISC interface address bus.
I
Digital supply voltage for 5V.
I/O
Master clock for external audio DAC (8.192MHz, 11.2896MHz, 12.288MHz,16.9344MHz,
and 18.432MHz).
O
Dual-purpose pin. AOUT is the audio interface serial data output.
I
Pins SEL-PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK for the
ES3210:
00=bypass PLL.
01=54MHz PLL.
10=67.5MHz PLL.
11=81MHz PLL.
I/O
Audio transmit bit clock.
O
Dual-purpose pin. ATFS is the audio interface transmit frame sync.
I
Pins SEL-PLL[1:0] select phase-lick loop(PLL) clock frequency CPUCLK for the
ES3210. See the SEL-PLL0 pin above for the sttings.
O
DRAM output enable (active low).
I
Audio interface serial data input.
I
Audio receive bit clock.
I
Audio interface receive frame sync.
I
TDM interface serial clock.
I
TDM interface serial data receive.
I
TDM interface frame sync.
O
DRAM column address strobe bank 0 (active low).
XL-SV320SL/SV305GD
XL-SV308BU
Definition
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