Interrupt Handler - Panasonic EB-GD93 Technical Manual

7.5. Interrupt Handler

The ARM CPU has two interrupts. FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt.
HERCULES has 16 interrupt sources. The interrupt handler assigns priorities to these interrupts and routes them to either the
FIQ or IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmasked
interrupt, if the CPU is in sleep mode.
The FIQ interrupt is reserved for the power supply fail priority interrupt. This interrupt comes from OMEGA chip INT1.
Interrupt Source
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
The interrupt priorities are programmed through interrupt level registers. The interrupt has 23 registers:
$FFFF:FA00
$FFFF:FA02
$FFFF:FA04
$FFFF:FA06
$FFFF:FA08
$FFFF:FA0A
$FFFF:FA0C
$FFFF:FA0E
$FFFF:FA2C
MCUK001001G8
Technical Guide
Interrupt Level Assignments
Description
Watchdog Timer INT
Timer 1 INT
Timer 2 INT
OMEGA fast interrupt
TPU frame INT
TPU page INT
SIM INT
UART modem / IRDA INT
Keyboard INT
RTC periodical timer INT
RTC Alarm / ULPD / I2C INT
ULPD gauge timer
External INT
SPI INT
DMA INT
API INT
Interrupt pending register
Mask interrupt register
IRQ source register
FIQ source register
IRQ source register (binary)
FIQ source register (binary)
Control Register
IRQ0 interrupt register
|
IRQ15 interrupt level register
Section 7
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Interrupt detection
Edge sensitive
Edge sensitive
Edge sensitive
Low Level sensitive (FIQ)
Edge sensitive
Edge sensitive
Edge sensitive
Low Level sensitive
Low Level sensitive
Edge sensitive
Low Level sensitive
Edge sensitive
Low Level sensitive
Edge sensitive
Low Level sensitive
Edge sensitive
Read only / Reset
Read / Write
Read only
Read only
Read only
Read only
Read / Write
Read / Write
Read / Write
HERCULES
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