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2-7 High Voltage Part
2-7-1 PWM REG Circuit
For the existing high voltage REG circuit (input voltage
variation type), a dynamic REG response is not provided. So
it is difficult for both beam linearity and uniformity in screen
size to be maintained on the screen with rapidly changing
beams.
A PWM (Pulse Width Modulation) type of high voltage,
however, provides the maintenance of beam linearity and
uniformity in screen size via a quick response to beam
change by performing sync lock every 1H line, and detecting
beam fluctuation at 1H line, and then controlling the IC
current of high voltage output circuit.
1. High Voltage Fluctuation Detect (DC Detect)
FBT pin 11 detects DC high voltage fluctuation. The
detected DC high voltage value is input to PWM IC471
pin1 through R473, VR471, R471, and then it is input to a
differential AMP circuit that differentiates the gap after
comparing with the reference voltage input to pin2.
2. High Voltage Fluctuation Detect (AC Detect)
To check AC high voltage fluctuation, the output from FBT
is detected by using a capacitor inside the high voltage
distributor. The detection of AC high voltage fluctuation,
a detection of dynamic beam current change is required in
order to keep beam linearity and uniformity in size.
Regarding the capacitor, a capacity of less than 3000P
should be applied to a PWM type. (The existing type
needs a capacity of about 6000P.) AC detect circuit
eliminates unnecessary high frequency by using C476,
D472. Also, AC gain is limited to + / - 0.7V (D472). This AC
gain is combined with the detection value of DC high
voltage fluctuation by using C478.
3. PWM IC OSC Sync Lock
A PWM type IC needs sync lock for PWM pulse and
horizontal scan line.
The standard time constant of OSC circuit is determined
by C487, R475 (PWM IC pins 5 and 6).
And the standard OSC frequency is about 27 kHz . The
horizontal frequency of scan line is 31.5kHz(NT),
31.25kHz(PAL), so sync lock for this horizontal frequency
should be performed using sync lock circuit. The sync lock
Samsung Electronics
circuit consists of Q481(Tr KSC815-Y), D479, D478, and
C492. The input AFC signal is connected to PWM IC pin 5
through D479 so that it can be negative Trig.
4. Dead Time (HV Protect)
Dead Time (PWM IN pin4) consists of C481, delays high
voltage for a certain time to soft start in power on, a x-ray
protection circuit. The voltage of Dead Time is detected
by FBT pin7 and through DC Feedback. The normal
voltage of Dead Time is +27V. When high voltage
increases, however, detected voltage is in proportion to
high voltage. Then, the detected voltage is applied to
ICR01S(TL431).
If the voltage is over 2.5V (normal:about 2.25V), TL431
turns ON, the base port of QR401S becomes low, and then
an emitter current flows. At this time, a high voltage
protection point is set. When QR401S turns ON, high
voltage is applied to PWM IC pin4 and then muted.
5. Output Circuit
The voltages, which are detected form an error detection
circuit of PWM IC (Differential AMP) and Dead Time, each is
applied to PWM conparator . Due to these detection coltages,
Q1, Q2 (Output TR) parallel operate. Q482 (External TR),
however, functions as a buffer; natches inpedance between
the output port of PWM IC and the final output TR(IRFS640).
The PWM pulse (applied to the final output FET (IRFS640
GATE) varies the IC current of high voltage TR(Q473) by
adjusting the load impedance of starage Trans (T431). Due to
this variation of current, the gain for Q473 emitter pulse
changes T444(FBT)makes this emitter pulse became high
voltage. Such change keeps both dynamic and static
changes fixed. The output waveform of high valtage TR
emitter is as shown in the figure below.
Alignment and Adjustments
2-33
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