Pin Functions; Ic307 Dat Signal Processor (Cxd2601Ao) - Sony DTC-670 Service Manual

Pin No.
Pin Name
vo
Description
t , 2
3
+6
7 , 8
9
A08,409
VDD
A I G A I 2
A l 3 , A l 4
XWE
vo
VO
o
o
RAM address A08, A09
5 V
RAM addrcss A10"A12
RAM address A13, Al4
RAM write enable signal
l 0
l l
t 2
l 3
t 4
xoE
XEAN
TSTI
XTIO
X T I I
o
o
I
o
I
RAM output enable signal
Extemal addressing bus intemrpt enable signal (Not in use)
Test pin (normally "L")
18.816 MHz crystal oscillator output
18.816 MHz crystal oscillator input
5
6
7
8
9
vss
XRST
CLKO
XCST
ATSY
I
vo
VO
I
GND
Reset pin (normally"H")
I8.816 MHz clock ouçut (Not in use)
SYEK (internal system clock) generation CLKO division timing signal (Not in use)
ATF sync signal input
20
2 l
) t
23
24
MCLK
DREF
SBPM
EXCK
SDSI
o
o
o
9.408 MHz clock ouput
Drum servo reference signal
Discrimination signal determining whether the subcode VO clock (EXCK) is accepted ("L": accept, "H":
ignore) (Not in use)
Subcode VO data transfer clock (DUTYSO)
Subcode scrial data input
25
26
27
28
29
sDso
SBSY
COPY
EMP
MUTE
o
o
o
o
I
Subcode serial data ouput
Subcode VO sync signal
Copy data output (Not in use)
Emphasis data ouput (Not in use)
Mute pin
30
3 l
32
33
34
MUTM
IJNLK
ERMN
SYMN
CHER
o
o
o
o
I
Mute discrimination signal ("H": muted)
RX PLL lock discrimination siglal ('H": locked)
Deæcs presence or absence ofRF ("H": RF present, "L" during REC)
Cl check result for RF C'H": OK) (Not in use)
Signal for discriminadng whether C2 is I or 2 times
(C2 + Cl + C2 orCl + C2) ("H": I time, "L": 2 times) (Not in use)
35
36
37
38
39
PLCK
TST2
RFDT
xcs
swP
VO
I
I
I
I
RF PLL clock output (Not in use)
Test pin (normally "L")
RF signal input
Subcode VO chip select C'L": select)
RF switching pulse ("L": A-CH, "H": B-CH)
Æ
4 l
42
43
44
vss
PIFC
REPB
REDT
TST4
o
o
o
I
GND
REC data PILOT/PCM discrimination signal ("H": PILOT, during playback: always "L")
Recordfulayback switching signal ("H": record)
Recording signal ouput, fixed "L" during playback
Test pin (normally "L')
45
6
47
$
PDO
AMPI
AMFO
Ptco
o
I
o
I
RX APLL PD ourput (comparalor output)
RX APLL oscillator cell amp input
RX APLL oscillator cell amp inverted ouput
RX APLL extemal VCO clock input
DTC-670
+10. PtN FUNCTTONS
lCIlO7 DAT Signal Èocossor (CXD2601AO!
This p'rocessor is an LSI to process recording and playback signals of the R-DAT system, in a single chip and provided with digital PLL, modem,
error corrcction circuit, digital VO, RAM control circuit, etc.
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