Ic Pin Function Description - Sony HCD-CP2A Service Manual

7-18. IC PIN FUNCTION DESCRIPTION

• MAIN BOARD IC802 CXP84332-224Q (SYSTEM CONTROLLER)
Pin No. Pin Name
1 A/B
2 TREBLE A
3
REC (DUB/HI-DUB)
4 C-XRST
5 AMP-S/B
6 AMP-MUTE
7 REC-BIAS
8 REC/PB
9 CAP-MOTOR-CON
10
CAP-MOTOR-H/L
11 TRIG CON (A)
12 TRIG CON (B)
13 BASE A
14 T-HALF (A)
15 T-PLAY (A)
16 T-SHUT (A)
17 T-SHUT (B)
18 T-PLAY (B)
19 TU-TUNED
20 TU-DATA
21 TU-CLK
22 TU-COUNT
23 TU-CE
24 RDS-DATA
25 RDS-ON
26 C/D
27 LCD DATA
28 LCD CLK
29 LCD CE
30 RESET
31 EXTAL1
32 XTAL1
33 VSS
34 TX
35 TEX
36 AVSS
37 AVREF
38 SIMUKE
39 B-HALF
40 KEY1
I/O
O Deck-A/B selection signal output to the HA12215F (IC306) "L": deck-A, "H": deck-B
I Jog dial pulse input from the rotary encoder (RV803 TREBLE) (A phase input)
O High speed dubbing control signal output to the HA12215F (IC306)
O Reset signal output to the CXD2587Q (IC101) and BA5974FP (IC102) "L": reset
O Standby on/off control signal output to the power amplifier (IC101, 201) "L": standby mode
O Muting on/off control signal output to the power amplifier (IC101, 201) "H": muting on
Recording bias on/off selection signal output to the HA12215F (IC306)
O
"L": bias on, "H": bias off
Recording/playback/pass selection signal output to the HA12215F (IC306)
O
"L": recording mode, "H": playback mode
O Capstan motor on/off control signal output terminal "H": motor on
High/normal speed selection signal output of the capstan motor
O
"L": normal speed, "H": high speed
O Deck-A side trigger plunger on/off control signal output
O Deck-B side trigger plunger on/off control signal output
I Jog dial pulse input from the rotary encoder (RV802 BASE) (A phase input)
I Detection input from the deck-A cassette detect switch "L": cassette in, "H": no cassette
I Detection input from the deck-A play detect switch "H": deck-A play
I Shut off detection signal input from the deck-A side reel pulse detector
I Shut off detection signal input from the deck-B side reel pulse detector
I Detection input from the deck-B play detect switch "H": deck-B play
I Tuning detection signal input from the tuner pack "L": tuned
O PLL serial data output to the tuner pack
O PLL serial data transfer clock signal output to the tuner pack
I PLL serial data input from the tuner pack
O PLL chip enable signal output to the tuner pack
RDS serial data input from the RDS decoder (IC803)
I
(Used for the AEP, UK and North European models only)
Power supply on/off control signal output of the tuner pack (+7V) and RDS decoder (IC803)
O
(Used for the AEP, UK and North European models only)
O Command data output to the liquid crystal display driver (IC800)
O Serial data output to the liquid crystal display driver (IC800)
O Serial data transfer clock signal output to the liquid crystal display driver (IC800)
O Chip enable signal output to the liquid crystal display driver (IC800)
System reset signal input from the reset signal generator (IC801) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
I Main system clock input terminal (4.19 MHz)
O Main system clock output terminal (4.19 MHz)
— Ground terminal
O Sub system clock output terminal (32.768 kHz)
I Sub system clock input terminal (32.768 kHz)
— Ground terminal (for A/D converter)
I Reference voltage (+5V) input terminal (for A/D converter)
I Destination setting terminal (A/D input)
I Detection input from the deck-B half detect switch "L": cassette in, "H": no cassette
Key input terminal (A/D input)
I
S800 to S807 (TUNING –/+, REC z, TAPE B M/m/x/Y, TUNER BAND keys input)
Description
"H": plunger on
"H": plunger on
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