Philips 32PFL8605H/12 Service Manual page 411

Circuit Diagrams and PWB Layouts
Clocks, JTAG, BBS-debug
Clocks, JTAG, BBS-debug
P02I
1 2
A
B
C
D
+3V3
1FR0
1
2
3
4 5
BM03B-SRSS-TBT
E
1FR1
BBS
1
CONTROL
2
3
DEBUG
4
FFS1
5 6
B4B-PH-SM4-TBT(LF)
F
1 2
Q551.1E LA 10. EN 411
3 4 5
7F10-3
BCM7206
CLOCKS
IFR0
9FR0 F7
DDR_EXT_CLK DDR_PLL_TEST
F23
DFR2 BYP_SYS9_CLK CLK27_OUT
F20
DFR4
BYP_RFM_PLLO
H23
DFR5
BYP_CPU_CLK
F22
DFR7 BYP_AVD_CLK
H22
DFR8
BYP_DSP_CLK VCXO_OBSRV
F24
DFR9 MON_3OT OBSRV_PLL
A26
CLK54_XTALP CLK54_XTALN
5
3FR1
RES
5K6
5FR0
3FR2
RES
680R 2u7
1FR3
1 3
54M
7F10-9
BCM7206
FFR7 EJTAG
3FR6 3FR7
RES
+3V3
4K7 4K7
C25
EJTAG_CE0 EJTAG_TRSTB
C24
EJTAG_CE1 EJTAG_TDI
FFR8 EJTAG_TDO
3FS3 3FS4
RES G26
+3V3
BSC_S_SCL EJTAG_TMS
G28
4K7 FFR9 4K7 BSC_S_SDA EJTAG_TCK
3FS5
FFS0
100R 3FS6
100R
Function EJTAG_CE0
Normal EJTAG 1
Internal test X
JTAG boundary scan 0
3 4 5
2010-Oct-01
6 7
F6
DFR1
AE9 9FR1
PCI-CLK-N-740X
AD10
DFR6
VCXO27A
G23
DFS0
G22
DFS1
B26
2FR0
RES RES
33p
+3V3 +3V3
D25
D24
E24 3FS2
B25 33R
A25
EJTAG_CE1
0
1
0
6 7
back to
div. table
P02I
8
1FR0 D1
1FR1 E1
1FR2 D8
1FR3 C5
2FR0 C5
A
2FR1 D4
2FR2 D6
2FR3 E2
3FR0-1 E6
3FR0-2 E6
3FR0-3 E7
3FR0-4 E7
3FR1 B4
3FR2 C4
B
3FR3 C4
3FR4 C6
3FR5 E6
3FR6 E3
3FR7 E4
3FR8 E2
3FR9 E2
3FS0 E7
3FS2 E6
C
3FS3 E3
3FS4 E4
3FS5 E3
3FS6 E4
5FR0 C5
7F10-3 A4
7F10-9 D4
9FR0 A4
9FR1 A6
D
DFR1 A6
DFR2 A4
DFR4 A4
DFR5 A4
1FR2
DFR6 A6
FFR0
1
FFR1
DFR7 A4
2
FFR2
3
DFR8 B4
FFR3
4
FFR4
5 DFR9 B4
FFR5
6
E
FFR6 DFS0 B6
7
+3V3 8
DFS1 B6
10
9
FFR0 E8
BM08B-SRSS-TBT
FFR1 E8
FFR2 E8
FFR3 E8
FFR4 E8
FFR5 E8
FFR6 E8
F
FFR7 E3
FFR8 E4
FFR9 E3
FFS0 E4
FFS1 E1
IFR0 A4
8
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2 2010-06-16
1 2010-02-05
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