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-4-
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Pin
No.
110
Signal name
I
Description
46
110
02
I
Data bus
47
110
D1
!
Data bus
48
110
DO
I
Data
bus
49
1/0
A1S
I
Address bus
so
I
110
I
A14
!
Address bus
S1
0
!
A13
I
Address bus
S2
0
A12
!
Address bus
S3
0
A11
I
Address bus
S4
1/0
I
A10
i
Address bus
55
0
i
A9
I
Address bus
S6
0
i
A8
j
Address bus
S7
110
I
A?
I
Address bus
S8
110
i
A6
I
Address
bus
I
S9
110
I
AS
\
Address bus
60
110
!
A4
Address bus
61
1/0
I
A3
!
Address bus
62
110
!
A2
Address bus
63
1/0
I
A1
I
Address bus
64
110
I
AO
l
Address bus
65
I
I
~
!
Reset input (Reset at
LOW)
I
I
Liquid
crystal
driver enable
sig-
66
0
I
E
nal
·
67
I
M
I
Timer
clock
input
68
I
LS'
Low battery detection
pin.
Low
when low battery.
Low
battery
symbol lighting volt-
69
0
CAU
age detection pin. (After turning
on the
symbol,
high
impedance.)
70
I
I
XTAL1
Oscillation circuit input
71
0
I
XTAL2
Oscillation circuit
output
72
-
I
GND
Power source
8
73
0
I
CLKOUT
Oscillation
clock output
I
74
I
-
vcc
Power
source
EB
75
0
VCNT
Liquid
crystal
power ON/OFF
SW signal
76
0
i
BZ
BUZZER
I
77
1/0
i
M1
I
ZBOCPU
machine
cycle
78
I
I
KON
CN KEY input
79
I
I
SFTIN
SHIFT KEY input
80
I
0
I
K01
I
Key strobe
Pin
No.
110
Signal
name
Description
1
0
K02
.
Key
strobe
2
0
K03
I
Key strobe
3
0
K04
I
Key strobe
4
0
KOS
Key strobe
s
0
K06
Key strobe
6
0
K07
I
Key strobe
7
0
KOS
Key strobe
8
0
K09
!
Key strobe
9
0
K010
Key strobe
10
I
IA1
Key input
11
I
IA2
Key
input
12
I
i
IA3
.
Key input
13
I
IA4
l
Key
input
14
I
I
AS
Key
input
1S
I
IA6
.
Key
i
n
put
16
I
I
A
?
I
Key input
17
I
IA8
Key input
18
110
MREQ
ZBOCPU memory
request
signal
19
110
IORQ
I
ZBOCPU
VO
request
signal
20
I
SlJSRQ
ZBOCPU bus request
signal
I
Expansion peripheral
reset out-
21
0
IORESET
put
(Active
high)
(40 pin expan-
1
sion bus output)
22
I
WAIT
i
ZBOCPU wait input
23
I
INT1
J
ZBOCPU maskable interrupt re-
quest
24
110
W'R
i
Z80CPU memory write signal
2S
110
RD
I
ZBOCPU memory read signal
Bank select address (When
26
110
BNK3
resetting,
domestic.lforeign
select signal)
27
110
BNK2
Bank select address
28
0
BNK1
I
Bank select address
29
0
BNKO
Bank select address
Expansion memory chip enable
30
0
CEROM2
signal (Outputted to 40 pin ex-
pansion bus)
1
Built-in system ROM chip enable
31
0
CEROM1
signal
32
-
GND
Reference voltage
Expansion memory chip enable
33
0
CERAM2
signal (Outputs to 40 pin expan-
sion
bus.)
34
0
I
CERAM1
Built-in RAM chip enable signal
35
I
I
182
J
11
pin ACK
36
I
181
J
11 pm DIN
37
0
I
XOUT
Cassette signal
output
38
I
XIN
Cassette signal input
39
0
I
F02
11 pin DOUT
40
0
F01
11
pin BUSY
41
110
D7
Data bus
42
110
i
06
1
Data bus
43
1/0
D5
I
Databus
44
110
04
I
Data
bus
45
110
D3
!
Data bus
CPU (LZ8413M} pin signal descriptions
s:-i:sraescriptions
!
--:~·
~·
. : ,.
-r-r-:
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