Sony STR-DN1000 Service Manual page 74

STR-DN1000
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3 7 63 1515 0
Pin No. Pin Name
D11 ACLKX2
D12, D13 DVDD
D14 EM_WAIT
D15 EM_OE#
D16 SPI0_ENA#
E1 ACLKR1
E2 ACLKX1
E3 UHPI_HD[21]
E4 DVDD
E5 VSS
E6 to E11 CVDD
E12 VSS
E13 DVDD
E14 UHPI_HD[8]
E15 EM_CS[2]#
E16 EM_RW
F1 AFSR1
F2 AFSX1
UHPI_HD[19],
F3, F4
UHPI_HD[20]
F5 to F12 VSS
UHPI_HD[10],
F13, F14
UHPI_HD[9]
F15 EM_CS[0]#
F16 EM_RAS#
G1 VSS
TE
L 13942296513
G2 RESET#
UHPI_HD[17],
G3, G4
UHPI_HD[18]
G5 CVDD
G6 to G11 VSS
G12 CVDD
UHPI_HD[12],
G13, G14
UHPI_HD[11]
G15 EM_BA[0]
G16 VSS
H1 UHPI_HD[16]
H2 CLKIN
H3 VSS
H4 UHPI_HD[31]
H5 CVDD
H6 to H11 VSS
H12 CVDD
UHPI_HD[14],
H13, H14
UHPI_HD[13]
H15 EM_A[10]
H16 EM_BA[1]
J1 OSCVSS
J2 OSCIN
J3 OSCOUT
J4 OSCVDD
www
J5 CVDD
J6 to J11 VSS
J12 CVDD
.
J13 UHPI_HD[15]
J14 DVDD
J15, J16 EM_A[1], EM_A[0]
74
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I/O
O Interruput signal output to the system controller
- Power supply terminal (+3.3V) (for IO)
I Not used
O Not used
I Chip enable signal input from the system controller
I Bit clock signal input from the digital audio interface receiver and HDMI receiver
O Bit clock signal output to the wireless transmitter and D/A converter
I/O Not used
- Power supply terminal (+3.3V) (for IO)
- Ground terminal
- Power supply terminal (+1.26V) (for core)
- Ground terminal
- Power supply terminal (+3.3V) (for IO)
I/O Not used
O Not used
O Not used
I L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
O L/R sampling clock signal output to the D/A converter
I/O Not used
- Ground terminal
I/O Not used
O Chip select signal output to the SD-RAM
O Row address strobe signal output to the SD-RAM
- Ground terminal
I Reset signal input from the system controller and reset signal generator
I/O Not used
- Power supply terminal (+1.26V) (for core)
- Ground terminal
- Power supply terminal (+1.26V) (for core)
I/O Not used
O Bank address signal output to the SD-RAM
- Ground terminal
I/O Not used
I Not used
- Ground terminal
I/O Not used
- Power supply terminal (+1.26V) (for core)
- Ground terminal
- Power supply terminal (+1.26V) (for core)
I/O Not used
O Address signal output to the SD-RAM
O Bank address signal output to the SD-RAM
- Ground terminal for oscillator
I System clock input terminal (25 MHz)
O System clock output terminal (25 MHz)
- Power supply terminal for oscillator
- Power supply terminal (+1.26V) (for core)
- Ground terminal
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y
- Power supply terminal (+1.26V) (for core)
i
I/O Not used
- Power supply terminal (+3.3V) (for IO)
O Address signal output to the SD-RAM
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2 9
8
Description
Q Q
3 6 7 1 3 1 5
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
"L": reset
m
9 9
9 9