S1L52502F24J000 (X2688A00) Gate Array(Dga) - Yamaha TYROS 2 Service Manual

Tyros2

S1L52502F24J000 (X2688A00) Gate Array(DGA)

PIN
NAME I/O
NO.
1 LV
DD
2 XDACK I
3 XDRAK I
4 XDREQ O
5 ATPGEN I
6 Vss
7 ENCA0 I
8 ENCB0 I
9 ENCA1 I
10 ENCB1 I
11 HV
DD
12 ENCA2 I
13 ENCB2 I
14 ENCA3 I
15 ENCB3 I
16 Vss
17 ENCA4 I
18 ENCB4 I
19 ENCA5 I
20 ENCB5 I
21 HV
DD
22 TSTEN I
23 XIDCS0 O
24 XIDCS1 O
25 XIDDOE O
26 Vss
27 HV
DD
28 XIDWR O
29 XIDRD O
30 XIDMACK O
31 IDMARQ I
32 Vss
33 IDD0 I/O
34 IDD1 I/O
35 IDD2 I/O
36 IDD3 I/O
37 HV
DD
38 IDD4 I/O
39 IDD5 I/O
40 IDD6 I/O
41 IDD7 I/O
42 Vss
43 IDD8 I/O
44 IDD9 I/O
45 IDD10 I/O
46 IDD11 I/O
47 HV
DD
48 IDD12 I/O
49 IDD13 I/O
50 IDD14 I/O
51 IDD15 I/O
52 Vss
53 LV
DD
54 SDRD0 I/O
55 SDRD1 I/O
56 SDRD2 I/O
57 SDRD3 I/O
58 Vss
59 SDRD4 I/O
60 SDRD5 I/O
61 SDRD6 I/O
62 SDRD7 I/O
63 LV
DD
64 SDRD8 I/O
65 SDRD9 I/O
66 SDRD10 I/O
67 SDRD11 I/O
68 Vss
69 SDRD12 I/O
70 SDRD13 I/O
71 SDRD14 I/O
72 SDRD15 I/O
73 LV
DD
74 SDRA0 O
75 SDRA1 O
76 SDRA2 O
77 SDRA3 O
78 Vss
79 LV
DD
80 SDRA4 O
81 SDRA5 O
82 SDRA6 O
83 SDRA7 O
84 Vss
85 SDRA8 O
86 SDRA9 O
87 SDRA10 O
88 SDRA11 O
89 LV
DD
90 SDRA12 O
91 SDRA13 O
92 XSDRWE O
93 XSDRRAS O
94 Vss
95 XSDRCAS O
96 XSDRCS0 O
97 XSDRCS1 O
98 SDRDQM O
99 LV
DD
100 SDRCLK O
101 XTCLR I
102 HV
DD
103 TESTRAM I
104 Vss
34
FUNCTION
Power supply +3.3V
CPU DMA acknowledge
CPU DREQ request acknowledge
CPU DMA request
ATPG test input
Ground
Encoder0 A input
Encoder0 B input
Encoder1 A input
Encoder1 B input
Power supply +5V
Encoder2 A input
Encoder2 B input
Encoder3 A input
Encoder3 B input
Ground
Encoder4 A input
Encoder4 B input
Encoder5 A input
Encoder5 B input
Power supply +5V
Test mode change
IDE chip select
IDE bus buffer DIR signal
Ground
Power supply +5V
IDE write signal
IDE read signal
IDE DMA acknowledge
IDE DMA request
Ground
IDE data bus
Power supply +5V
IDE data bus
Ground
IDE data bus
Power supply +5V
IDE data bus
Ground
Power supply +3.3V
SDRAM data bus
Ground
SDRAM data bus
Power supply +3.3V
SDRAM data bus
Ground
SDRAM data bus
Power supply +3.3V
SDRAM address output
Ground
Power supply +3.3V
SDRAM address output
Ground
SDRAM address output
Power supply +3.3V
SDRAM address output
SDRAM write signal
SDRAM row address strobe
Ground
SDRAM column address strobe
SDRAM chip select
SDRAM data enable
Power supply +3.3V
SDRAM clock
Test counter clear
Power supply +5V
RAM test mode
Ground
PIN
NAME I/O
NO.
105 HV Power supply +5V
DD
106 LEDD0 O
107 LEDD1 O
Port/Test output
108 LEDD2 O
109 LEDD3 O
110 Vss Ground
111 LV Power supply +3.3V
DD
112 XTA22I I XTAL input terminal
113 Vss Ground
114 XTA22O O XTAL output terminal
115 LV Power supply +3.3V
DD
116 HV Power supply +5V
DD
117 LEDD4 O
118 LEDD5 O
Port/Test output
119 LEDD6 O
120 LEDD7 O
121 Vss Ground
122 VCOI I VCO clock input
123 HV Power supply +5V
DD
124 PDOUT O PLL phase comparator output
125 Vss Ground
126 XRESET I Reset signal input
127 EXTWCI I External synchronization WC input
128 SDIN I Digital sound input
129 SDOUT O Digital sound output
130 HV Power supply +5V
DD
131 XDSPCS0 O DSP6 chip select
132 XDSPCS2 O DSP chip select (reserve)
133 XDSPCS1 O DSP7 chip select
134 Vss Ground
135 AUDIOIN0 I
Audio data input
136 AUDIOIN1 I
137 AUDIOUT0 O Audio data output
138 LV Power supply +3.3V
DD
139 AUDIOUT1 O
140 AUDIOUT2 O Audio data output
141 AUDIOUT3 O
142 Vss Ground
143 AUDIOUT4 O
144 AUDIOUT5 O Audio data output
145 AUDIOUT6 O
146 LV Power supply +3.3V
DD
147 HV Power supply +5V
DD
148 CK512 O FS512 clock
149 FS256 O FS256 clock
150 FS128 O FS128 clock
151 Vss Ground
152 XFS64 O FS64 clock (reverse)
153 ALRCK O System WC (FS)
154 XSSYNC O DSP synchronizing signal output
155 HV Power supply +5V
DD
156 Vss Ground
157 LV Power supply +3.3V
DD
158 HV Power supply +5V
DD
159 XDLCS O Data buffer enable
160 XLCDCS0 O
LCD driver chip select
161 XLCDCS1 O
162 Vss Ground
163 CD0 I/O
164 CD1 I/O
CPU data bus
165 CD2 I/O
166 CD3 I/O
167 LV Power supply +3.3V
DD
168 CD4 I/O
169 CD5 I/O
CPU data bus
170 CD6 I/O
171 CD7 I/O
172 Vss Ground
173 CD8 I/O
174 CD9 I/O
CPU data bus
175 CD10 I/O
176 CD11 I/O
177 LV Power supply +3.3V
DD
178 CD12 I/O
179 CD13 I/O
CPU data bus
180 CD14 I/O
181 CD15 I/O
182 Vss Ground
183 LV Power supply +3.3V
DD
184 CA1 I
185 CA2 I
CPU address input
186 CA3 I
187 CA4 I
188 Vss Ground
189 CA5 I
190 CA6 I
CPU address input
191 CA7 I
192 CA12 I
193 LV Power supply +3.3V
DD
194 CA13 I
CPU address input
195 CA16 I
196 XCCS5 I
CPU chip select
197 XCCS6 I
198 Vss Ground
199 XCRD I CPU read signal
200 XCWR I CPU write signal
201 XCIRQ O
CPU interrupt request
202 XFTMIRQ1 O
203 LV Power supply +3.3V
DD
204 XFTMIRQ2 O
CPU interrupt request
205 XFTMIRQ3 O
206 FSPLAY O FS count signal
207 SCANEN I Scan enable input
208 Vss Ground
DM: IC25
FUNCTION
MO
TR
OWNE
BEDIE
MODE