LG KM330 Service Manual page 26

Audio CODEC
Support HE-AAC decode
Wavetable synthesis with up to 64 tones
Advanced wavetable synthesizer capable of generating simulated stereo
Wavetable including GM full set of 128 instruments and 47 sets of percussions
PCM Playback and Record
Digital Audio Playback
Audio Interface and Audio Front End
Supports I2S interface
High resolution D/A Converters for Stereo Audio playback
Stereo analog input for stereo audio source
Analog multiplexer for StereoAudio
FM Radio Recording
Stereo to Mono Conversion
3.1.5 General Description
Figure 3-2 details the block diagram of MT6229. Based on a dual-processor architecture,
MT6229 integrates both an ARM7EJ-S core and 2 digital signal processor cores. ARM7EJ-S
is the main processor that is responsible for running high-level 2G to 2.75G protocol software
as well as multi-media applications. Digital signal processors handle the MODEM algorithms
as well as advanced audio functions. Except for some mixed-signal circuitries, the other
building blocks in MT6229 are connected to either the microcontroller or one of the digital
signal processor. Specifically, MT6229 consists of the following subsystems:
Microcontroller Unit (MCU) Subsystem - includes an ARM7EJ-S RISC processor and its
accompanying memory management and interrupt handling logics.
Digital Signal Processor (DSP) Subsystem - includes 2 DSP cores and their accompanying
memory, memory controller, and interrupt controller.
MCU/DSP Interface - where the MCU and the DSPs exchange hardware and software
information.
Microcontroller Peripherals - includes all user interface modules and RF control interface
modules.
Microcontroller Coprocessors - runs computing-intensive processes in place of
Microcontroller.
DSP Peripherals - hardware accelerators for GSM/GPRS/EGDE channel codec.
Multi-media Subsystem - integrates several advanced accelerators to support multi-media
applications.
Voice Front End - the data path for converting analog speech from and to digital speech.
Audio Front End - the data path for converting stereo audio from stereo audio source
Video Front End - the data path for converting video signal to NTSL/PAL format.
Baseband Front End - the data path for converting digital signal from and to analog signal of
RF modules.
Timing Generator - generates the control signals related to the TDMA frame timing.
Power, Reset and Clock subsystem - manages the power, reset, and clock distribution
inside MT6229.
Details of the individual subsystems and blocks are described in following Chapters.
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