LG 65UH8500 Service Manual page 87

Clock for F16
F16_RESET_SW
MAIN Clock(24MHz)
SW9200
8pF
JTP-1127WEM
XIN_F16
C9200
F16_XTAL_LoadCap_Default
1 2
3 4
8pF 33
R9269
XO_F16
C9201
F16_XTAL_LoadCap_Default
Move to x-tal side
(TSMC Recommend)
System Clock for Analog block(24MHz)
C9200-*1 6.8pF
F16_XTAL_LoadCap_OLED_E6
C9201-*1 6.8pF
F16_XTAL_LoadCap_OLED_E6
EAN63146601
SPI Flash
IC9200
MX25L6435EM2I-10G
R9206
10K
OPT
CS# VCC
1 8
MSPI_CS_M
SERIAL_FLASH_MX
SO/SIO1 HOLD#/SIO3
2 7
MSPI_MISO_M
WP#/SIO2 SCLK
R9205 1K
3 6
FLASH_WP_F16
R9207
10K GND SI/SIO0
4 5
* MX25L6435EM2I-10G : IWP (Individual Write Protect) supported
UART0 For system
UART1 For FRC
DEBUG_F16_UART DEBUG_F16_UART
+3.3V_NORMAL +3.3V_NORMAL
P9200 P9201
12507WS-04L 12507WS-04L
R9201 R9208
1 1
4.7K 4.7K
R9202 R9209
33
2 UART_RX_0 2
R9203 R9210
3 3
4.7K 4.7K
R9204 R9211
33
4 4
UART_TX_0
5 5
C9202 C9203
0.1uF 0.1uF
16V 16V
+3.3V_NORMAL
F16 Option
Low High
BIT0 Main SoC M16 H15
F16_BIT0
BIT1 Display LCD OLED
F16_BIT1
BIT2 Resolution 4K 8K
F16_BIT2
BIT5 Reserved
F16_BIT3
BIT6 Tx Frame Rate 120Hz 60Hz
F16_BIT4
F16_BIT5
F16_BIT6
BIT(3/4) Display Type BIT(7/8) DIVISION Type
F16_BIT7
00 Vx1 DE 00 NON DIVISION
F16_BIT8
01 Vx1 Sync 01 2 DIVISION
10 EPI 49" 10 4 DIVISION
11 EPI 55" 11 5 DIVISION
Low High F16_BIT9
BIT9 DDR Vendor SS Micron F16_BIT10
BIT10 AV_BOX Non_AV_BOX AV_BOX
BIT(11/12) Module Maker
F16_BIT11
00 LGD
F16_BIT12
01 INNORUX
10 BOE
11 LGD (75"~)
F16_BIT13
F16_BIT14
Low High
BIT13 Vx1 OSD input Blended OSD Separate OSD F16_BIT15
* This option operates when BIT6 is 60Hz
If BIT6 is 120Hz, Vx1 OSD type is separate OSD.
Low High
Tx 8lane,
BIT14 Vx1 Lane Tx 16lane
Video 8lane
Vx1 Tx OFF
BIT15 50%
Pre-emphasis (Default)
* BIT14 option is for Vx1 Eye improvement in case of over 1M cable.
In case of over 1M cable, select Low, Others select High.
+3.3V_NORMAL
Low High
BIT16 Reserved
BIT17 Reserved
F16_BIT16
F16_BIT17
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
F16 Reset
+3.3V_NORMAL
R9214
10K
F16_RESET_MICOM
R9212 C9204
270K 10uF
OPT
EAN63765801
+3.3V_NORMAL
SERIAL_FLASH_SPANSION
IC9200-*1
S25FL164K0XMFI010
CS VCC
1 8
SO/IO1 HOLD/IO3
2 7
WP/IO2 SCK
3 6
VSS SI/IO0
4 5
R9213
10K
C9205
0.1uF
16V
MSPI_SCLK_M
MSPI_MOSI_M
33
UART_RX_1
33
UART_TX_1
JTAG for F16
JTAG0 for SYSTEM
+3.3V_NORMAL
TP9210
TP9211 TDI_0
TMS_0
TP9212
TCK_0
TP9213
TP9214 TDO_0
TP9215 TRST_0
TP9216
SPI/I2C Live Boot Test
TDI_0
TDO_0
TMS_0
TCK_0
TRST_0
TDI_1
TDO_1
TMS_1
TCK_1
TRST_1
UART_RX_0
UART_TX_0
UART_RX_1
UART_TX_1
To TCON To TCON
(Not used)
(PCB Bottom)
I2C_SCL2
To M16/H15
I2C_SDA2
A_SPI_CS_S
SPI_MOSI_S
To M16/H15
SPI_MISO_S
SPI_SCLK_S
MSPI_CS_M
MSPI_MOSI_M
To S-Flash memory
MSPI_MISO_M
MSPI_SCLK_M
JTAG1 for FRC
+3.3V_NORMAL
TP9200
TP9201 TDI_1
TMS_1
TP9202
TCK_1
TP9203
TP9204 TDO_1
TP9205 TRST_1
TP9206
SPI/I2C Serial Flash Boot Test
IC9000
LGE1124(F16)
L2
TDI0 FRC_LRSYNC
M1
TDO0 L_VSIN_LD
M2
TMS0 L_VSOUT_LD
L1
TCK0 L_VSOUT_LD1
M3
TRSTN0 DIM0_MOSI
DIM0_SCLK
J2
TDI1 DIM1_MOSI
K1
TDO1 DIM1_SCLK
K2
TMS1 DIM2_MOSI
J1
TCK1 DIM2_SCLK
K3
TRSTN1 DIM3_MOSI
DIM3_SCLK
G1
UART0_RXD PWM0
H1
UART0_TXD PWM1
G2
UART1_RXD PWM2
H2
UART1_TXD
PWM_IN
AM29
I2C_SCL_M1 EPI_EO
AN29
I2C_SDA_M1 EPI_GCLK
AL26
AR9201 I2C_SCL_M2 EPI_MCLK
33
AK26
I2C_SDA_M2 EPI_VST
F23
AR9203
I2C_SCL_S
33
F24
I2C_SDA_S XTALI
XTALO
D24
R9222 33
SPI_CS_S
E23
R9223 33
SPI_MOSI_S PORES_N
E24
R9224 33
SPI_MISO_S TMODE0
D23
R9225 33
SPI_SCK_S TMODE1
TMODE2
B25
R9226 33
MSPI_CS_M TMODE3
B24
R9227 33
MSPI_MOSI_M CID0
A24
R9228 33
MSPI_MISO_M CID1
A25
R9229 33
MSPI_SCK_M TRIGGER
BOOT_MODE
AM27
TSPI_CS_M SYNC_ALIGN
AM28
TSPI_MOSI_M
AN28
TSPI_MISO_M GPIO00
AN27
TSPI_SCK_M GPIO01
GPIO02
A19
SSPI_CS0_M GPIO03
B19
SSPI_CS1_M GPIO04
C19
SSPI_CS2_M GPIO05
D19
SSPI_MOSI_M GPIO06
C20
SSPI_SCK_M GPIO07
GPIO08
D20
SSPI0_CS_S GPIO09
A21
SSPI0_MOSI_S GPIO10
B21
SSPI0_SCK_S GPIO11
GPIO12
C21
SSPI1_CS_S GPIO13
D21
SSPI1_MOSI_S GPIO14
C22
SSPI1_SCK_S GPIO15
GPIO16
D22
SSPI2_CS_S GPIO17
A23
SSPI2_MOSI_S GPIO18
B23
SSPI2_SCK_S GPIO19
GPIO20
AN31
OSPI_MOSI_M GPIO21
AM31
OSPI_SCLK_M GPIO22
AM30
OSPI_SCLK_S GPIO23
AN30
OSPI_MOSI_S GPIO24
GPIO25
AG27
DELOCK GPIO26
AG26
HSLOCK GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
PAGE 92
AH28
AK29
AH29
R9234 33
L/DIM0_VS_F16
L/D_F16
AJ29
AF28
R9235 33 L/DIM0_MOSI_F16
L/D_F16
AG28
R9236 33 L/DIM0_SCLK_F16
L/D_F16
AD28
AE28
AJ28
AJ27
AJ26
AJ25
AG29
3D_SYNC_RF
AE29
TP9207
AF29
AD29
R9242 10K
AL28
F16_EPI_EO F16_EPI_EO
AK27
F16_EPI_GCLK F16_EPI_GCLK
AL29
FOR EPI control
F16_EPI_MCLK F16_EPI_MCLK
AK28
F16_EPI_GST F16_EPI_GST
AM25
XIN_F16
AN25
XO_F16
R9230 33
SPI_DL_MODE
SPI_DL_MODE
R9231 33
AM26 F16_RESET_MICOM
C9207
0.01uF
AG24
AG25
TMODE
AH24 Normal Operation : 1
(Default)
(Internal Pull Up)
AH25
AK24
AJ24
Chip ID
AH27
0 0 : 4K (Default)
AK25
R9232 10K
AH26
BOOT MODE
- 0 : Default
- 1 : Not Used
E25
F16_BIT0
F25
C24
F16_BIT13
C23
F16_BIT1
E21
F16_BIT2
F21
F16_BIT3
E20
F16_BIT4
F20
F16_BIT5
E19
F16_BIT6
F19
F16_BIT7
D18
F16_BIT8
E18
F16_BIT9
F18
F16_BIT10
D17
F16_BIT11
E17
F16_BIT12
F17
R9233
33
F16_CONNECT_DET F16_CONNECT_DET
E1
DATA_FORMAT_0_F16 DATA_FORMAT_0_F16
E2
DATA_FORMAT_1_F16 DATA_FORMAT_1_F16
F1
LOCKn_IN LOCKn_IN
F2
PMIC_RESET PMIC_RESET
E3
F16_BIT14 LOCKAn_MONITOR
E4
F16_BIT15
F3
LOCKAn_MONITOR
F4
F16_BIT16
G3
F16_BIT17
G4
J3
J4
K4
L3
GPIO used only for SIC
L4
TP9208
M4
TP9209
M16 2015.11.23
92 99
F16_SPI,UART,GPIO
LGE Internal Use Only