Sony STR-DA9000ES Service Manual page 127

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• DIGITAL BOARD IC2251 CXD9782R (DSP2)
Pin No. Pin Name
VDDI
1
EXTIN
2
WMD1, WMD0
3, 4
5 MOD1
MOD0
6
VSS
7
8 XRST
VSS
9
SCKOUT
10
VDDI (PLL)
11
12 SYNC
13 to 15 PAGE2 to PAGE0
16 PLOCK
BTACK
17
18 VDDE
VSS
19
D31 to D29
20 to 22
23 A17
VSS
24
TE
L 13942296513
25, 26 SDO3, SDO4
SDI1, SDI2
27, 28
LRCKI1
29
VSS
30
31, 32 D28, D27
A16
33
A15
34
SDI3
35
36 L2
VDDI
37
BCKI1
38
SDI4
39
40 MS
41, 42 A14, A13
D26, D25
43, 44
VSS
45
BCKI2
46
47, 48 FS2, FS1
SPDIF
49
A12
50
www
D24 to D22
51 to 53
VDDE
54
.
55 VSS
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I/O
—
Power supply terminal (+2.6V)
I
Master clock signal input terminal Not used
I
External memory wait mode setting terminal Fixed at "H" in this set
Operation mode setting terminal "L": enhanced mode, "H": normal mode
I
Fixed at "H" in this set
Operation mode setting terminal "L": single chip mode, "H": can not use
I
Fixed at "L" in this set
—
Ground terminal
I System reset signal input from the main system controller "L": reset
—
Ground terminal
O
Internal serial clock signal output terminal Not used
—
Power supply terminal (+2.6V) (for PLL)
I Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
O
External memory page selection signal output terminal Not used
O
Internal PLL lock signal output terminal Not used
O
Boot mode state display signal output terminal Not used
— Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
O
Address signal output terminal Not used
—
Ground terminal
O Audio serial data output to the DC cut digital filter
I
Audio serial data input from the DSP1
I
L/R sampling clock signal (44.1 kHz) input from the DSP
—
Ground terminal
I/O Two-way data bus with the S-RAM
O
Address signal output terminal Not used
O
Address signal output to the S-RAM
I
Audio serial date input from the DSP
— Not used
—
Power supply terminal (+2.6V)
I
Bit clock signal (2.8224 MHz) input from the DSP
I
Audio serial data input from the DSP
Master/slave setting terminal "L": internal clock, "H": external clock
I
Fixed at "L" in this set
O Address signal output to the S-RAM
I/O
Two-way data bus with the S-RAM
—
Ground terminal
I
Bit clock signal (2.8224 MHz) input terminal Not used
I Sampling frequency selection signal input terminal Not used
I
SPDIF signal input terminal Not used
O
Address signal output to the S-RAM
I/O
Two-way data bus with the S-RAM
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y
—
Power supply terminal (+3.3V)
i
— Ground terminal
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2 9
8
Description
Q Q
3 6 7 1 3 1 5
co
.
STR-DA9000ES
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9
127