1
1
2
2
3
3
14 13 12 11
9
8
1
2
3
4
5
6
7
+3.3V(D)
6
8
7
IC103
TC7WU04U
DUAL2-INPUT
NAND GATE
4
3
2
1
EX_CLK
ZD101
28 27 26 25 24 23 22 21 20 19 18
SCLKN2
LRCLKN2
29
CLKIN
30
VA
34
AGND
35
RESET
36
39
40
Figure 15 BLOCK DIAGRAM (4/10)
– 15 –
D0
17
D1
16
15
D2
14
D3
IC101
DGND2
13
CS493264
VD2
12
DSP
11
D4
D5
10
D6
9
8
D7
7
41
42
43
44
1
2
4
5
6
SD-AT1000
EMAD0
EMAD1
EMAD2
EMAD3
+2.5V(A)
EMAD4
EMAD5
EMAD6
EMAD7
_DSP_SCCLK