Only For Training And Service Purposes - LG CU575 Service Manual

3.9.7 MSM6260 microprocessor subsystem
■ Industry standard ARM926EJ-S embedded microprocessor subsystem
❏ 16 kB instruction and 16 kB data cache
❏ Instruction set compatible with ARM7TDMI®
❏ ARM version 5TEJ instructions
❏ Higher performance 5 stage pipeline, Harvard cached architecture
❏ Higher internal CPU clock rate with on-chip cache
■ Java hardware acceleration
■ Enhanced memory support
■ 75 MHz and 90 MHz bus clock for SDRAM
■ 32-bit SDRAM
■ Dual memory buses separating the high-speed memory subsystem (EBI1) from low-speed
peripherals (EBI2) such as LCD panels
■ 1.8 V memory interface support for EBI1 and 1.8V or 2.6V memory interface support for EBI2
■ NAND FLASH memory interface
❏ 8/16-bit data I/O width NAND flash support
❏ 1- or 4-bit ECC
❏ 512-byte/2KB page-size support
❏ 2 chip selects supported for NAND Flash
❏ Boot from NAND
❏ Low-power SDRAM (LP-SDRAM) interface
■ Internal watchdog and sleep timers
3.9.8 Supported interface features
■ USB On-the-Go core supports both slave and host functionality
■ Three universal asynchronous receiver transmitter (UART) serial ports
■ USIM controller (via UART)
■ Integrated 4-bit secure digital (SD) controller for SD and Mini SD cards
■ Parallel LCD interface
■ General-purpose I/O pins
■ External keypad interface
3.9.9 Supported multimedia features
■ Provide additional general purpose MIPS by using:
❏ Two QDSP4000s
❏ Dedicated hardware accelerators and compression engines
■ Improve Java, BREW, and game performance
❏ Integrated Java and 2D/3D graphics accelerator with Sprite engine
■ Enable various accessories via USB host connectivity.
❏ Integrated USB host controller functionality
■ Enable compelling visual and audio applications.
Copyright © 2007 LG Electronics. Inc. All right reserved.

Only for training and service purposes

3. TECHNICAL BRIEF
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LGE Internal Use Only