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MAIN PWB CIRCUIT DIAGRAM (4/8)
L501
BLM21A601S
R518
12
QSS
100R
TU500
R504
AGC
1
100R
11
SCL_5V
R506
TU
2
100R
10
SDA_5V
R521
S500
AS
3
10k
9
C522
SCL
4
AMMONO_MAIN
8
220n
25V
SDA
5
7
C508
6
NC
6
470n
63V
C509
L502
VS
7
+5V_TU_IF
5
BLM21A601S
10n
50V
C506
R507
NC/ADC
8
5k6
4
10n
50V
R502
+33V
VST
9
22k
3
IF2
3
GND
IF2
10
2
2
IN2
OUT2 5
S501
SF_63962
IF1
Z500
1
IN1
OUT1 4
IF1
11
1
MAIN PWB ASS'Y
(4/8)
VE-20224628
L504
+5V_TU_IF
22u
SIOMAD
NC
13
R508
SCL
TAGC
14
100R
C510
X500
75R
SDA
REF
15
R513
22p
4MHz
50V
C511
TOP
VAGC
16
R517
63V
2k2
470n
47R
R516
BC848B
AUD
CVBS
17
C516
Q501
100n
25V
DGND
AGND
18
C524
100n
C512
25V
R512
AFD
VPLL
19
330R
100n
25V
L503
15MOHM TAKILACAK
DEEM
VP
20
BLM21A601S
C515
100n
FMPLL
AFC
21
25V
22k
R515
SW01=H L'
OP1
OP2
22
L/Lp
SW01=L BG,DK,I,L
R527
6k8
+5V_IF
25V
100p
VIF2
SIF1
23
4
OUT1
IN1 1
C520
K9356M
Z501
C521
5
OUT2
IN2 2
VIF1
SIF2
24
GND
3
100p
25V
IC500
Q502
1k
BC848B
R525
R530
C519
100R
1k
100n
+5V_IF
25V
R523
MAIN PWB CIRCUIT DIAGRAM (5/8)
+5V
CVBS_SC1
CVBS_IF
CVBS_SC2
C523
22u
+10V
50V
SVHS_C
+5V_TU_IF
75R
+12V
R630
75R
R614
IF1
IF2
R522
33k
L/Lp
(No.YA352)2-11
2-12(No.YA352)
Video Matrix
63V
IC600
100n
C601
1 INPUT1
INPUT8
20
SDA_5V
100R
2 DATA
GND2
19
R602
C602
3 INPUT2
OUTPUT6
18
100n
63V
R603
SCL_5V
100R
4 CLOCK
OUTPUT5
17
R634
+10V
100k
C612
5 INPUT3
OUTPUT4
16
MODULE_C
75R
R636
100n
100k
R631
16V
R635
16V
100k
100n
6 INPUT4
OUTPUT3
15
C611
R637
100k
C603
7 PROG
OUTPUT2
14
CVBS_IF
C607
100n
33p
63V
50V
8 INPUT5
OUTPUT1
13
L600
9 VCC
GND1
12
22u
C600
100u
16V
10 INPUT6
INPUT7
11
C609
SVHS_Y
100n
16V
MAIN PWB ASS'Y
VE-20224628
63V
100n
CVBS_BAV
C606
R626
Q603
470R
BC848B
R629
75R
C
R605
Q600
470R
BC848B
R610
75R
Y/CVBS
Q601
470R
R608
BC848B
SC2_OUT_V
75R
R613
+10V
C610
C613
S600
R_SC2
100n
100n
16V
16V
R619
Q602
470R
BC848B
R617
75R
SC1_OUT_V
(5/8)
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