Yamaha RX-V2400 Service Manual page 56

RX-V2400/RX-V2400RDS/DSP-AX2400
RX-V1400/RX-V1400RDS/HTR-5690/DSP-AX1400
IC512: D601A002PYP180 (DSP P.C.B)
Decoder
No. Name
1 GP0[4]/(EXT_INT4)
2 GP0[6]/(EXT_INT6)
3 CVDD
4 VSS
5 DVDD
6 GP0[5]/(EXT_INT5)
7 GP0[7]/(EXT_INT7)
8 CLKS1
9 DVDD
10 VSS
11 CVDD
12 TINP1/AHCLKX0
13 TOUT1/AXRO[4]/AXR1[11]
14 CVDD
15 VSS
16 CLKX0/ACLKX0
17 TINP0/AXRO[3]/AXR1[12]
18 TOUT0/AXRO[2]/AXR1[13]
19 ACLKR0
20 AXRO[1]
21 AFSX0
22 CVDD
23 VSS
24 AFSR0
25 DVDD
26 VSS
27 AXRO[0]
28 AHCLKR0
29 CVDD
30 VSS
31 FSX1
32 DX1
33 CLKX1
34 VSS
35 CVDD
36 CLKR1
37 DR1
38 FSR1
39 VSS
40 CVDD
56
EMIF32 L2 Cache/
Memory
4 Banks
McASP1
64K Bytes
Total
McASP0
(4-Way)
McBSP1
McBSP0
L2
I2C1 Enhanced
Memory
DMA
Controller
DA610:
I2C0
(16 channel)
192K Bytes
Timer 1
DA601:
64K Bytes
Timer 0
GP1
GP0
R2 ROM
512K
Bytes
HPI16
Total
I/O Function
IOZ
General purpose I/O0 port 4
IOZ General purpose I/O0 port 6
S 1.2V power supply
GND Ground
S 3.3V power supply
IOZ
General purpose I/O0 port 5
IOZ
General purpose I/O0 port 7
I
McBSP1 external clock source
S 3.3V power supply
GND Ground
S 1.2V power supply
I
Timer 1 Input
O
Timer 1 Output
S
1.2V power supply
GND
Ground
IOZ McASP0 Transmission BCLK
I Timer 0 Input
O Timer 0 Output
IOZ
McASP0 Reception BCLK
IOZ
McASP0 Transmission/reception data 1
IOZ
McASP0 Transmission LRCLK
S
1.2V power supply
GND Ground
IOZ McASP0 Reception LRCLK
S 3.3V power supply
GND
Ground
IOZ
McASP0 Transmission/reception data 0
I
McASP0 Reception MCLK
S 1.2V power supply
GND Ground
IOZ McBSP1 Transmission Frame Sync (Input in SPI slave state)
O/Z McBSP1 Transmission data
IOZ
McBSP1 Transmission clock (Input in SPI slave state)
GND
Ground
S 1.2V power supply
IOZ McBSP1 Reception clock
I McBSP1 Reception data
IOZ McBSP1 Reception Frame Sync
GND Ground
S
1.2V power supply
Digital Signal Processors
L1P Cache
Direct Mapped
4K Bytes Total
C67x TM CPU
Control
Instruction Fetch
Registers
Instruction Dispatch
Control
Instruction Decode
Logic
Data Path A Data Path B
Test
A Register File B Register File
In-Circuit
Emulation
Interrupt
.L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t
Control
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers