Sony HCD-GTX999 Service Manual page 56

HCD-GTX999
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3 7 63 1515 0
Pin No. Pin Name
62 VSS
63, 64 EM_D (10), EM_D (9)
65 CVDD
66 EM_D (8)
67 EM_WE_DQM (1)
68 DVDD
69 VSS
70 EM_CLK
71 EM_CKE
72 VSS
73 DVDD
EM_A (11_12),
74 to 76
EM_A (9_10), EM_A (8_9)
77 CVDD
78 VSS
79 EM_A (7_8)
80 EM_A (6_7)
81 DVDD
82 VSS
EM_A (5_6),
83, 84
EM_A (4_5)
85 CVDD
86 EM_A (3_4)
87 VSS
EM_A (2_3),
88, 89
EM_A (1_2)
90 CVDD
91 EM_A (0_1)
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L 13942296513
92 DVDD
93 EM_A (10_11)
94 EM_BA (1)/EM_A (_0)
95 VSS
96 EM_BA (0)
97 EM_CS (0)
98 EM_RAS
99 VSS
100 EM_CS (2)
101 CVDD
102 EM_RW
103 DVDD
104 EM_OE
105 B
106 VSS
107 A
108 I2CO_SCL/BOOT
109 VSS
110 GPIO/BOOT
111 I2CO_SDA/BOOT
112 DVDD
113 SDTI
114 VSS
115 SDTO_O
116 BD_CLK
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117 BD_SENS
118 VSS
119 BD_GAIN-SW
.
120 BD_XLAT
121 BD_DATA
122 BD_SCOR
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I/O
- Ground terminal
I/O Two-way data bus with the SDRAM, fl ash memory and USB interface
- Power supply terminal (+1.2V)
I/O Two-way data bus with the SDRAM, fl ash memory and USB interface
O Write enable signal output to the SDRAM
- Power supply terminal (+3.3V)
- Ground terminal
O Clock signal output to the SDRAM
O Clock enable signal output to the SDRAM
- Ground terminal
- Power supply terminal (+3.3V)
O Address signal output to the SDRAM and fl ash memory
- Power supply terminal (+1.2V)
- Ground terminal
O Address signal output to the SDRAM and fl ash memory
O Address signal output to the SDRAM, fl ash memory and USB interface
- Power supply terminal (+3.3V)
- Ground terminal
O Address signal output to the SDRAM, fl ash memory and USB interface
- Power supply terminal (+1.2V)
O Address signal output to the SDRAM, fl ash memory and USB interface
- Ground terminal
O Address signal output to the SDRAM, fl ash memory and USB interface
- Power supply terminal (+1.2V)
O Address signal output to the SDRAM, fl ash memory and USB interface
- Power supply terminal (+3.3V)
O Address signal output to the SDRAM and fl ash memory
Bank address signal output to the SDRAM, and address signal output to the fl ash memory
O
and USB interface
- Ground terminal
O Bank address signal output to the SDRAM
O Chip select signal output to the SDRAM
O Row address strobe signal output to the SDRAM
- Ground terminal
O Chip select signal output to the memory decoder
- Power supply terminal (+1.2V)
- Not used
- Power supply terminal (+3.3V)
O Output enable signal output to the fl ash memory and USB interface
O Address decode signal output to the memory decoder
- Ground terminal
O Address decode signal output to the memory decoder
I/O Two-way I2C serial clock signal bus with the system controller
- Ground terminal
- Not used
I/O Two-way I2C serial data bus with the system controller
- Power supply terminal (+3.3V)
I Audio serial data input from the A/D converter and D/A converter
- Ground terminal
O Audio serial data output to the A/D converter and D/A converter
O Serial data transfer clock signal output to the digital servo
I Internal status (SENSE) input from the digital servo
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- Ground terminal
y
O Gain switch signal output to the motor/coil driver
i
O Serial data latch pulse output to the digital servo
O Serial data output to the digital servo
I Sub-code sync (S0+S1) detection signal input from the digital servo
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2 9
8
Description
Q Q
3 6 7 1 3 1 5
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9