Kenwood DDX8017 Service Manual page 28

DDX8017/8027/8027Y
DDX8037/8047/8067
MICROCOMPUTER'S TERMINAL DESCRIPTION
Disc Controller Microcomputer: MN103S71F (X37: IC4)
Pin No. Pin Name
1 SW_2
2 SW_3
3 CDON
4 VDD3
5 VSS
6 FG
7 SW_4
8,9 FADR17,18
10 FADR11
11 FADR9
12 VDD15
13 FADR8
14,15 FADR13,14
16 NWE
17,18 FADR16,15
19 DRAMVDD15
20 DRAMVSS
21 VSS
22 FADR12
23~30 FADR7~0
31 VSS
32 VDD3
33~40 FDT0~7
41 NCE
42 FADR10
43 NOE
44 MMOD
45 NRST
46 VSS
47 SCLOCK
48 SDATA
49 TxD/EXTRG0 I/O
50 RxD/EXTRG1 I/O
51 VDD3
52 OSCI
53 OSCO
54 VSS
28
I/O Application
I 8cm Ej-STOP, Lo-START detection
I Lo-START detection
O CD-LD ON
- VDD (3.3V)
- VSS
I Motor FG input
I Lo-END detection
O Address output to FLASH
O Address output to FLASH
O Address output to FLASH
- VDD (1.5V)
O Address output to FLASH
O Address output to FLASH
O Right signal output to FLASH
O Address output to FLASH
- DRAM power supply (1.5V)
- VSS for DRAM
- VSS
O Address output to FLASH
O Address output to FLASH
- VSS
- VDD (3.3V)
I/O Data input/output with FLASH
O Chip select signal output to FLASH
O Address output to FLASH
O Read signal output to FLASH
I Test mode switching signal
I Reset input
- VSS
I/O Dwire clock terminal
I/O Dwire data terminal
Serial transmission/
Dwire trigger terminal
Serial reception/
Dwire trigger terminal
- VDD (3.3V)
I Oscillation input (16.897849MHz)
O Oscillation output (16.897849MHz)
- VSS
Pin No. Pin Name I/O
55 OFS_TE O
56 DRV1 O
57 DRV2 O
58 DVDON O
59 STEP_A O
60 STEP_B O
61 Lo/Ej O
62 LO.MUTE O
63 VSS -
64 DRV.MUTE O
65 BMS O
66 LIM-SW I
67 Gain_SW O
68 FEPCK O
69 FEPDT O
70 FEPEN O
71 DRAMVSS -
72 DRAMVDD15 -
73 DRAMVDD33 -
74 VDD3 -
75 FG I
76 TX O
77 VDD15 -
78 VSS -
79 TSTSG O
80 VFOSHORT O
81 JLINE O
82 BDO I
83 OFTR I
84 AVSSD -
85 ROUT O
86 LOUT O
87 AVDDD -
88 VCOF I
89 TRCRS I
90 AVDDC -
91 WBLIN I
92 CSLFLT I
93 RFDIF I
Application
CD TE offset cancel output
Drive output for spindle drive
Focus balance adjustment output
DVD-LD ON
Thread control output A
Thread control output B
Lo/Ej control terminal
Lo/Ej mute terminal
VSS
Driver mute control
Spindle short brake control
LIM-SW detection
PDIC Gain switching
FEP clock output
FEP data output
FEP enable signal
VSS for DRAM
DRAM power supply (1.5V)
DRAM power supply (3.3V)
VDD (3.3V)
Motor FG input
Output for digital OUT
VDD (1.5V)
VSS
EQ calibration signal
Not used.
J-line setting output
Dropout signal input
Off-track signal input
VSS for analog
MASH Rch audio output
MASH Lch audio output
VDD (3.3V) for analog
JFVCO control voltage
Track loss generation signal input
VDD (3.3V) for analog
WBL input
Not used
Not used