Table of Contents
Advertisement
EN 46
8.
3139 785 33120
IC7203 - 96KHz Sampling 24-bit stereo audio ADC
BLOCK DIAGRAM
V DDA
d th
16
1
V INL
3
V INR
13
DATAO
11
BCK
12
WS
PIN DESCRIPTION AND CONFIGURATION
SYMBOL
PIN
V
1
left channel input
INL
V
2
reference voltage
ref
V
3
right channel input
INR
V
4
negative reference voltage
RN
V
5
positive reference voltage
RP
SFOR
6
data format selection input
PWON
7
power control input
SYSCLK
8
system clock 256, 384, 512 or 768f
V
9
digital supply voltage
DDD
V
10
digital ground
SSD
BCK
11
bit clock input/output
WS
12
word select input/output
DATAO
13
data output
MSSEL
14
master/slave select
V
15
analog ground
SSA
V
16
analog supply voltage
DDA
IC Description
V SSA
V RP
V RN
15
5
4
ADC
SD
ADC
SD
DIGITAL
INTERFACE
Figure 8-11
DESCRIPTION
s
V ref
SYSCLK
2
UDA1361TS
DECIMATION
CLOCK
FILTER
CONTROL
DC-CANCELLATION
FILTER
handbook, halfpage
V INL
1
V ref
2
V INR
3
V RN
4
UDA1361TS
V RP
5
6
SFOR
PWON
7
SYSCLK
8
8
9
V DDD
10
V SSD
14
MSSEL
7
PWON
6
SFOR
MGT451
V DDA
16
V SSA
15
14
MSSEL
13
DATAO
12
WS
11
BCK
V SSD
10
V DDD
9
MGT452
Advertisement
Table of Contents
