Md2250 - Sony DPP-SV55 Service Manual

MD2250 (FMD)
JPEG PROCESSOR
—TOP VIEW—
109
110
115
120
125
130
135
140
144
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 I VREFP1 37 — GND
2 I VREFN1 38 I/O UD0
3 — A.GND 39 I/O UD1
4 I VIDEOIN 40 I/O UD2
5 — A.V 41 I/O UD3
CC
6 — A.V 42 I/O UD4
CC
7 I IREFV 43 I/O UD5
8 I IREFC 44 I/O UD6
9 — A.GND 45 I/O UD7
10 — A.GND 46 I/O LD0
11 I SIN 47 I/O LD1
12 — A.V 48 I/O LD2
CC
13 I VREFN2 49 — V
CC
14 I VREFP2 50 — GND
15 — GND 51 I/O LD3
16 O Y2 52 I/O LD4
17 O Y3 53 I/O LD5
18 O Y4 54 I/O LD6
19 O Y5 55 I/O LD7
RAS
20 O Y6 56 O
CAS
21 O Y7 57 O
MWE
22 O C0 58 O
23 O C1 59 O CKE
24 O C2 60 O SDCLK
25 — V 61 — V
CC CC
26 — GND 62 — GND
DQMU
27 O C3 63 O
DQML
28 O C4 64 O
29 O C5 65 O MA0
30 O C6 66 O MA1
31 O C7 67 O MA2
PXOE
32 O 68 O MA3
33 O VBLK 69 O MA4
34 O HBLK 70 O MA5
35 O FLD 71 O MA6
36 — V 72 O MA7
CC
DPP-SV55 V2
72
70
65
60
55
50
45
40
37
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
73 — V 109 — GND
CC
74 — GND 110 I HA1
75 O MA8 111 I HA2
76 O MA9 112 I HA3
CS
77 O MA10 113 I
RD
78 O MA11 114 I
WR
79 O MA12 115 I
DREQ
80 O MA13 116 I
DACK
81 O MA14 117 I
MRESET INT
82 I 118 I
STDBY
83 I 119 I/O HIN
84 O TEST 120 I/O VIN
85 — V 121 I/O FI
CC
86 I LFT 122 I/O PXCLK
87 I MCLKI 123 — V
CC
88 O MCLKO 124 — GND
89 — GND 125 I YIN0
90 I/O HD0 126 I YIN1
91 I/O HD1 127 I YIN2
92 I/O HD2 128 I YIN3
93 I/O HD3 129 I YIN4
94 I/O HD4 130 I YIN5
95 I/O HD5 131 I YIN6
96 I/O HD6 132 I YIN7
97 I/O HD7 133 O Y0
98 — V 134 O Y1
CC
99 — GND 135 — A.V
CC
100 I/O HD8 136 O CVBS
101 I/O HD9 137 O IREFY
102 I/O HD10 138 — A.GND
103 I/O HD11 139 — A.GND
104 I/O HD12 140 I IREFC
105 I/O HD13 141 O S
106 I/O HD14 142 — A.V
CC
107 I/O HD15 143 — V
CC
108 — V 144 — GND
CC
INPUTS
CS
: CHIP SELECT
DACK
: TRANCE PERMISSION PULSE
HA1 - HA3 : ADDRESS
IREFC : REFERENCE CURRENT SETTING
IREFS, IREFV : REFERENCE VOLTAGE DECOUPLING
IREFY : REFERENCE CURRENT SETTING
LFT : PLL LOW PASS FILTER
MCLKI : CRYSTAL OSCILLATOR
MRESET
: RESET
PXOE
: YC DATA SYNC SIGNAL TURNS TO HIGH IMPEDANCE
RD
: READ PULSE
SIN : ANALOG COMPOSITE C DATA WHEN Y/C SEPARATE
STDBY
: STANDBY MODE
VIDEOIN : ANALOG COMPOSITE DATA
VREFN1, VREFN2 : REFERENCE VOLTAGE DECOUPLING
VREFP1, VREFP2 : REFERENCE VOLTAGE DECOUPLING
WR
: WRITE PULSE
YIN0 - YIN7 : TEST
OUTPUTS
C0 - C7 : C DIGITAL OUTPUT
CAS : COLUMN ADDRESS SELECTOR
CKE : CLOCK ENABLE OF SDRAM
CVBS : ANALOG COMPOSITE
DQML
: MASK BIT CONTROL OF LOWER 8BIT DATA BUS
DQMU
: MASK BIT CONTROL OF UPPER 8BIT DATA BUS
DREQ
: TRANCE DEMAND PULSE
FLD : FIELD RECOGNITION SIGNAL
HBLK : HORIZONTAL SYNC SIGNAL
INT
: LOW LEVEL WHEN EACH MODE COMPLETE
MA0 - MA14 : ADDRESS LINE OF SDRAM
MCLKO : CRYSTAL OSCILLATOR
MWE
: WRITE ENABLE
PXCLK : SAMPLING CLOCK
RAS : LOW ADDRESS SELECTOR
S : ANALOG C SIGNAL WHEN SVIDEO OUTPUT
SDCLK : CLOCK OUTPUT TO SDRAM
TEST : TEST
VBLK : VERTICAL SYNC SIGNAL
Y0 - Y7 : Y DIGITAL OUTPUT
INPUTS/OUTPUTS
FI : FIELD RECOGNITION SIGNAL
HD0 - HD15 : BI-DIRECTIONALLY DATA BUS
HIN : HORIZONTAL SYNC SIGNAL
LD0 - LD7 : LOWER 8BIT DATA OF SDRAM
UD0 - UD7 : UPPER 8BIT DATA OF SDRAM
VIN : VERTICAL SYNC SIGNAL
PDIUSBP11APW.118 (PHILIPS)
USB TRANSCEIVER
TOP VIEW
MODE 1 14 V
CC
OE
2 13 VMO/FSEO
RCV 3 12 VPO
VP 4 11 D+
VM 5 10 D_
SUSPND 6 9 SPEED
GND 7 8 NC
2
OE
9
10
SPEED
D_
13
11
VMO/FSEO
D+
12
VPO
+
3
RCV
_
4
VP
5
VM
INPUTS
MODE : MODE
OE
: OUTPUT ENABLE
SPEED : EDGE RATE CONTROL
SUSPND : SUSPEND
VMO/FSEO : DIFFERENTIAL DRIVER
VPO : DIFFERENTIAL DRIVER
OUTPUTS
RCV : RECEIVE DATA
VM : GATED VERSION OF D+
VP : GATED VERSION OF D_
INPUTS/OUTPUTS
D+ : DATA+
D_ : DATA_
OTHER
NC : NO CONNECTION
6-5
IC