1
QQ
3 7 63 1515 0
A
No.
Pin Name
99
QCLK
100 VDDI
101 VSS
102 EXCLK
103 OVDDE3
104 PH1
105 NC
106 AVS1
107 AVD1
B
108 CPO
109 NC
110 VCI
111 AVS2
112 AVD2
113 NC
114 PH2
115 PLLEN
116 OVDDE4
117 DCLK
C
118 OVSS1
119 DCLKP
120 VDDI
TE
L 13942296513
D
E
www
F
146
1
http://www.xiaoyu163.com
2
I/O
O
Video clock output
−
VDD for Core (+ 2.5 V)
−
Digital ground
I
Video clock input in external PLL use
−
VDD for I/O (+ 3.3 V)
O
Signal output 1 for external PLL comparator
−
Not used
−
Analog ground for PLL
−
Analog VDD for PLL (3.3 V)
O
Built-in PLL charge pump output
−
Not used
I
Built-in PLL VCO input
−
Analog ground for PLL
−
Analog VDD for PLL (3.3 V)
−
Not used
O
Signal output 2 for external PLL comparator
I
Built-in PLL/external PLL selection
−
VDD for I/O (+ 3.3 V)
I
27 MHz clock input
−
Digital ground
I
DCLK polarity setting pin
−
VDD for Core (+ 2.5 V)
x
ao
y
.
i
DVD-V8000
2
http://www.xiaoyu163.com
3
8
Pin Functions
Q Q
3
6 7
1 3
u163
.
3
4
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
m
co
4
9 9
2 8
9 9