Sharp LC-19LE430E Service Manual page 69

The device is controlled and configured via a hardware control interface.
The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK fs rates. The audio interface operates in slave
mode.
The WM8524 has a 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected.
The device is available in a 16pin TSSOP.
FEATURES
· High performance stereo DAC with ground referenced line driver
· Audio Performance
- 106dB SNR (.A-weighted.)
- -91dB THD @ -1dBFS
· 120dB mute attenuation
· All common sample rates from 8kHz to 192kHz supported
· Hardware control mode
2
· Data formats: LJ, RJ, I S
· Maximum 1mV DC offset on Line Outputs
· Pop/Click suppressed Power Up/Down Sequencer
· AVDD and LINEVDD +3.3V ±10% allowing single supply
· 16-lead TSSOP package
· Operating temperature range: -40°C to 85°C
APPLICATIONS
· Consumer digital audio applications requiring 2Vrms output
- Games Consoles
- Set Top Box
- A/V Receivers
- DVD Players
- Digital TV
1.6 U501 (TMDS251PAGR TQFP64)
Description
The TMDS251 is a 2-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 2 DVI or HDMI ports to be
switched to a single display terminal. Four TMDS channels, one hot plug detector, and a digital display control (DDC) interface are supported on each port.
Each TMDS channel supports signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.
The input port is enabled by configuring source selectors, S1 and S2. When an input port is selected, the TMDS inputs are connected to the TMDS outputs
through a 2-to-1 multiplexer, the MOSFET between the input DDC channel and the output DDC channel is turned on, and the HPD output follows the state
of the HPD_SINK. The other input port is inactive with disconnected input terminations, disconnected TMDS inputs to the outputs, disconnected DDC
inputs to the outputs, and the HPD outputs are low state. Check the source selection look up table for the details of port selections.
When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with standard TMDS terminations, all internal
MOSFETs are turned off to disable the DDC links, and all HPD outputs are connected to the HPD_SINK. This allows the initiation of the HDMI physical
address discovery process.
Termination resistors (50-Ω), pulled up to VCC, are integrated at each TMDS receiver input. External terminations are not required. A precision resistor is
connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard.
The TMDS251 provides two levels of receiver input equalization for different ranges of cable lengths. Each TMDS receiver owns frequency responsive
equalization circuits. When EQ sets low, the receiver supports the input connection in short range HDMI cables. When EQ sets high, the receiver supports
the input connection in long range HDMI cables. The TMDS251 supports power saving operation. When a system is under standby mode and there is no
digital audio/visual content from a connected source, the 3.3-V supply voltage, VCC, can be powered off to minimize power consumption from the TMDS
inputs, outputs, and internal switching circuits. The HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, VDD, to maintain
the system hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The device is characterized for
operation from 0°C to 70°C.
LC-19LE430E/UK, LC-22LE430E/UK, LC-26LE430E/UK, LC-32LE430E/UK
2008-03-14
69