Harman Kardon AVR125 Service Manual page 41

AVR125
X0, X1 RSTX
5
X0, X1A
EI
SIN0
SOT0
SCK0
SIN1, 2
SOT1, 2
SCK1, 2
AVCC
AVRH. L
AVSS
ADTG
AN0 to 7
PWC0
PWC1
PWC2
8
P00
P07
P00 to P07 (8): Provided with input pull-up resistor setting register
P10 to P17 (8): Provided with input pull-up resistor setting register
P40 to P47 (8): Provided with open-drain setting register
P70 to P75 (6): Provided with open-drain setting register
P76 to P77 (2): Open-drain
Note: In the figure above, the I/O port shares the pins with each internal functional block. When the pins
are used as internal module pins, they cannot be used as I/O port pins.
BLOCK DIAGRAM
Clock control
circuit
RAM
ROM
2
OS
Communication
prescaler
2
UART
I/O expanded
serial
interface x 2
channels
A/D converter
(10 bits)
16-bit PWC
3 channels
8 8 8
P10 P20 P30
P17 P27 P37
Fig. 1.1 Block Diagram (MB90470)
CPU
core
2
F MC-16LX family
I/O port
8 8 8
P40 P50 P60
P47 P57 P67
1-6
41
Interrupt controller
8-/16-bit PPG
8-/16-bits UD counter
µPG
Chip select
I/O timer
16-bit input capture x 2
16-bit output conveyer x 6
16-bit free-run timer
16-bit reload timer
x 2 channels
2
I C interface
External interrupt
8 8 8 4
P70 P80 P90 PA0
P77 P87 P97 PA3
harman/kardon
PPG0, 1
PPG2, 3
PPG4, 5
AIN0, 1
BIN0, 1
ZIN0, 1
EXTC
MT00
MT01
CS0, 1, 2, 3
IN0, 1
OUT0, 1, 2,
3, 4, 5
TIN0
TOT0
SCL
SDA
8
IRQ0 to 7