2. Block Diagram
Data
R/W
C67x+ CPU
Data
R/W
Program
I/O
INT
Fetch
Program
Cache
32K Bytes
32
I/O
Interrupts
MAX0
Out
D1
64
D2
Memory
64
Controller
CSP
256
PMP
DMP
32
32
HighúPerformance
Crossbar Switch
32
32
CONTROL
MAX1
dMAX
Program/Data
RAM
192
192K Bytes
Program/Data
ROM Page1
256
256K Bytes
Program/Data
ROM Page2
256
256K Bytes
Program/Data
ROM Page3
256
256K Bytes
32
32
32
Events
In
EMIF
Peripheral Interrupt and DMA Events
14
JTAG EMU
McASP0
32
16 Serializers
32
32
McASP1
6 Serializers
32
32
McASP2
2 Serializers
32
DIT Only
32
32
32
32
32
32
32
SPI1
SPI0
I2C0
I2C1
RTI
PLL