Marantz sr4500 Service Manual page 31

IC41 : H8S2398 pin port I/O
mode = 7
65 VSS I VSS
66 P60/_DREQ0 I/O NJW1157DATA
67 VSS I VSS
68 VSS I VSS
69 P61/_TEND0 I/O NJW1157CLK
70 P62/_DREQ1 I/O NJW1157LATCH -
71 P63/_TEND1 I/O N.C.
P27/PO7/TIOCB5/
72 I/O FLRA_ON
TMO1
P26/PO6/TIOCA5/
73 I/O N.C.
TMO0
P25/PO5/TIOCB4/
74 I/O SURR_ON
TMCI1
P24/PO4/TIOCA4/
75 I/O AVSS
TMRI1
P23/PO3/TIOCD3/
76 I/O _HEAT_DET
TMCI0
P22/PO2/TIOCC3/
77 I/O _STANDBY
TMRI0
78 P21/PO1/TIOCB3 I/O _HP_DET
79 P20/PO0/TIOCA3 I/O HP_ON
80 VCL I VCL
81 _RES I _RST
82 NMI I NMI
83 _STBY I _STBY
84 VCC I Vcc
85 XTAL I XTAL
86 EXTAL I EXTAL
87 VSS I VSS
88 PF7/<B I/O SEL-
89 VCC I Vcc
90 PF6 I/O SEL+
91 PF5 I/O _STBY LED
92 PF4 I/O _RSFL
93 PF3 I/O VOL-
94 PF2 I/O VOL+
95 PF1 I/O CTS
96 PF0 I/O RTS
97 P50/TxD2/_IRQ4 I/O OSDDATA
98 P51/RxD2/_IRQ5 I N.C
99 VSS I VSS
100 VSS I VSS
101 P52/SCK2/_IRQ6 I/O OSDCLK
P53/_ADTRG/
102 I/O _RSTFL
_IRQ7
103 AVCC I AVCC
104 Vref I VREF
105 P40/AN0 I KEY0
106 P41/AN1 I KEYBÒ
107 P42/AN2 I KEY2
108 P43/AN3 I N.C.
109 P44/AN4 I P_LINE_FAIL
110 P45/AN5 I MODE
111 P46/AN6/DA0 I N.C.
112 P47/AN7/DA1 I N.C.
113 AVSS I VSS
114 VSS I VSS
P17/PO15/TIOCB2/
115 I/O SB_ON
TCLKD
P16/PO14/
116 I/O RC_OUT
TIOCA2
P15/PO13/TIOCB1/
117 I/O N.C.
TCLKC
P14/PO12/
118 I/O N.C.
TIOCA1
P13/PO11/TIOCD0/
119 I/O KILLIR
TCLKB
P12/PO10/TIOCC0/
120 I/O N.C.
TCLKA
P11/PO9/TIOCB0/
121 I/O N.C.
_DACK1
P10/PO8/TIOCA0/
122 I/O RC_IN
_DACK0
123 MD0 I MD0
124 MD1 I MD1
125 MD2 I MD2
126 PG0 I/O _FCS
127 PG1 I/O _RSTDSP
128 PG2 I/O _SCS
Name STBY Port Setting Note
set use Act. init
- - - - GND
- O - L NJW1157/CS42418 Data Input
- - - - GND
- - - - GND
- O - L NJW1157/CS42418 Clock Input
O - L NJW1157 Latch Input
- O L L Open
- O H L Front Speaker On/Off
- O - L Open
- O H L SURR/CNT Speaker On/Off
- O H L Power Amp±B_L_Sel
Power Amp Heat sink
- I H -
TempDetect
- O L L Standby Power
I L - HP Jack Detect
-
- O H L Head Phone On
- - - -
- - L - Reset
- - - - Fix H(At the time of the un-use)
- - L H FixH
- - - - +5V
- - - - Xtal(20M)
- Xtal(20M)
- - -
- - - - GND
- I - - Front Select. Encoder
- - - - +5V
- I - - Front Select. Encoder
L O L H Standby LED On
- O L L Front FL Driver
- I - - Front Vol. Encoder
I Front Vol. Encoder
- - -
- I - - UART
H O - H UART
- O - L NJU3430 Data Input
- I - - Pull Down 10k
- - - - GND
- - - - GND
- O - L NJU3430 Clock Input
- O L L Reset FL Driver
- - - - +5V
- - - - +5V
- AD - - Front Key
- AD - - Front Key
- AD - - Front Key
- I - - Pull Up 47k
AD Emergency Protection
- - -
- AD - - CPU mode
- I - - Open
- AD - - Pull Down 47k
- - - - GND
- - - - GND
- O H L Surroud Back On: H / Off: L
- O - L RC BUS Output
- O - - Pull Up 47k
- O - L Open
L O H L Kill to IR input signal.
- O - L Open
- O - L Open
- T_IN ↑↓ - IR In for RC-5
- YES - - +5VL
- YES - - Fix H
- YES - - Normal :H, Boot :L
- O L H DSP Chip Enable
O L L DSP Reset
-
- O L H DSP Chip Enable
43
IC81 : NJU3430FG1
R S T
R ESET
Instruction
D ec oder
SI
CS 8bits
Line
Shift
C L K Address
R e g .
Counter
R S
Timing State Address
Gen. Reg. Selector
Read
OSC
1 C R Display
Address
OSC . Control
OSC Counter
2
V
D D
V
S S
V
F DP
N o . S Y M B O L I/O
5 7 V - P o w e r S o u r c e
D D
4 9 V - G N D
S S
V F D D r i v i n g P o w e r S o u r s e
4 8 V -
F D P
V
D D
C R O s c i l l a t i o n T e r m i n a l
5 0 O S C I
1
External R and C connect to these terminals.
(Target f
5 1 O S C O
2
Serial Clock Input Terminal
5 4 C L K I The serial data input synchronizing the rise edge of this
terminal.
C h i p S e l e c t T e r m i n a l
5 3 C S I W h e n t h e C S t e r m i n a l i s " H " t h e s e r i a l d a t a i n p u t i s n o t
a v a i l a b l e .
S e r i a l D a t a I n p u t T e r m i n a l
5 5 S I I
The data input is MSB first.
Register Selection Signal Input Terminal
5 6 R S I RS="0" : Instruction Register
R S = " 1 " : D a t a R e g i s t e r
R e s e t T e r m i n a l R S T = " L " : R e s e t
- E a c h A d d r e s s
- E a c h R A M D a t a
5 2 R S T I
- D i s p l a y D i g i t s
- C o n t r a s t C o n t r o l
-All Display Off
-All Outputs are "L"
6 1 t o 6 4 , Segment Output Terminals (Internal Pull-down
S to S O
1 3 5
1 t o 3 1 R e s i s t a n c e )
3 2 t o 4 7 T 1 to T 1 6 O Timing Output Terminals (Internal Pull-down Resistance)
6 0 M K 1
O Icon Output Terminals (Internal Pull-down Resistance)
5 9 M K
2
Output Port Terminal
5 8 P O
1
T h i s t e r m i n a l i s s u i t a b l e f o r L E D .
M K R AM Icon
M K
16x2 bit D r i v e r
C G R AM Segment
S
35x8 bit D r i v e r
Port
P
D r i v e r
C G R O M
8,400bit
D D R A M
16x8 bit
Timing
T
D r i v e r 1
F U N C T I O N
: V = + 3 . 0 t o 5 . 5 V
D D
: V = 0 V
S S
- 2 0 V t o V - 4 5 V
D D
= 3 6 0 k H z )
O S C
: (00) H
: Unfixed
: 1 6 - d i g i t
: 8/16 Dury
44
~ M K
1 2
~ S
1 35
1
T
~
1 6