Table of Contents
Advertisement
XR-A880, XR-A770
LC78622NE (CD ASSY : IC8301)
• CD DSP IC
•
Block Diagram
DEFI
1
Slice level
control
EFMIN
10
Sync
FSEQ
22
detection EFM
demosulation
CLV+
12
CLV Digital
servo
CLV–
13
V/*P
14
PW
49
Sub core
SBCK
51
separation
QCRC
SBSY
47
SFSY
50
*CS
63
WRQ
53
Microcomputer
Interface
SQOUT
55
*CQCK
57
COIN
56
RWC
54
15 16 17
•
Pin Function
N
. o
P
n i
N
a
m
e
/ I
O
1
D
E
I F
I
D
2
T
I A
I
3
P
D
O
O
−
4
V
V
S
S
P
5
S I
E
T
I A
−
6
V
V
D
D
7
F
R
I A
−
8
V
S
S
D
9
E
F
M
O
O
S
1
0
E
F
M
N I
I
1
1
T
E
S
T
2
I
e T
1
2
C
L
V
+
O
i D
C
1
3
C
L
V
–
O
R
1
4
V
* /
P
O
O
1
5
H
F
L
I
T
1
6
T
E
S
I
T
1
7
T
O
F
F
O
T
1
8
T
G
L
O
T
1
9
J
P
+
O
T
T
2
0
J
P
–
O
66
9
6
4
3
5
7
21
VCO clock
oscillator
clock control
General
Servo
purpose port
commander
20
19
58
18
34 24
25 26 27 28
e
e f
t c
d
e
e t
t c
o i
n
s
g i
n
a
( l
D
E
) F
n i
p
e T
t s
n i
p
t u
p
E
x
e t
n r
l a
V
C
n I
e t
n r
l a
V
C
L
L
p
n i
s
P
D
O
o
u
p t
t u
n I
e t
n r
l a
V
C
V
C
O
f
e r
q
u
e
i g i
a t
s l
s y
e t
m
g
o r
u
n
d
p
n i
M
u
t s
E
F
M
s
g i
n
l a
c i l
e
e l
e v
c l
o
n
r t
l o
E
F
M
s
g i
n
l a
t s
n i
p
t u
p
n i
A
p
l l u
d -
o
w
n
e r
s
t s i
c s
m
t o
r o
c
o
n
r t
l o
o
u
p t
t u
a
n
b
e
s
t e
o t
h t
e r
- e
a v
u l
e
o
u
p t
t u
o
u
g
h
s
r e
o v
p /
h
a
s
e
c
o
n
r t
l o
a
u
o t
m
u
p t
u
s t
a
h
g i
h
l
v e
l e
d
r u
n i
g
o r
u
g
h
a r
k c
d
e
e t
t c
o i
n
s
g i
n
l a
n i
p
t u
p
n i
a r
k c
n i
g
e
r r
r o
s
g i
n
l a
n i
p
t u
p
n i
T
a r
k c
n i
g
o
f f
o
u
p t
t u
p
n i
a r
k c
n i
g
g
a
n i
s
w
c t i
h
n i
g
o
u
p t
t u
p
n i
a r
k c
u j
m
p
o
u
p t
t u
h
e r
- e
a v
u l
e
o
u
p t
t u
s i
a
s l
o
p
o
s s
b i
20
59
64 11 32 33 62
23 8
2k × 8-bits
RAM
C1, C2 error detection
& correcting Flag
Processing
Crystal oscillation
system generator
29
48
60 61 46 52
45
44 43 39 41 35
F
u
n
t c
o i
n
t u
p
n i
(
M
u
t s
b
e
c
o
n
n
e
c
e t
d
o t
0
n i
A
p
l l u
d -
o
w
n
e r
s
t s i
r o
s i
b
l i u
i - t
O
c
o
n
r t
l o
p
h
a
s
e
c
o
m
p
r a
t a
r o
o
u
O
g
o r
u
n
d
p
n i
M
u
t s
b
e
c
o
n
n
e
c
e t
c
r u
e r
t n
a
d
u j
t s
m
e
t n
e r
s
t s i
r o
c
o
n
O
p
o
w
r e
s
u
p
p
y l
p
n i
n
y c
a r
n
g
e
a
d
u j
t s
m
e
t n
b
e
c
o
n
n
e
c
e t
d
o t
0
. V
o
u
p t
t u
p
n i
n i
p
t u
p
n i
r o
s i
b
l i u
i - t
. n
M
u
t s
b
e
c
o
n
n
e
c
e t
y b
m
c i
o r
p
o r
c
e
s s
r o
c
o
m
m
a
n
. d
a
c i t
s
w
c t i
h
n i
g
m
o
n
t i
r o
o
u
p t
t u
p
s
r e
o v
a
o l
w
e l
e v
. l
T
h
s i
s i
a
S
c
h
m
t t i
n i
p
u
. t
h
s i
s i
a
S
c
h
m
t t i
n i
p
u
. t
n I
c
e r
a
s
e
h t
e
g
a
n i
w
h
e
n
o l
. w
e l
w
h
e
n
s
p
e
f i c
e i
d
y b
m
c i
o r
p
o r
c
RAM address
generator
Interpolation
30
C2F
mute
Digital
DOUT
31
output
Digital
attenuator
8 × oversampling
digital-filter
1-bit DAC
L. P. F
40
37 42 38 36
V
w
h
e
n
u
n
u
s
e
d
. )
. n
M
u
t s
b
e
c
o
n
n
e
c
e t
d
o t
0
. V
p t
t u
p
n i
d
o t
0
. V
n
e
t c
o i
n
p
n i
d
o t
0
. V
n i
e
s s
r o
c
o
m
m
a
n
. d
Hide quick links:
Advertisement
Chapters
Table of Contents
